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| h8/3627 series h8/3627 hd6433627, hd6473627 h8/3626 hd6433626 h8/3625 hd6433625 h8/3624s hd6433624s h8/3623s hd6433623s h8/3622s HD6433622S hardware manual ade-602-174 rev. 1.0 3/11/99 hitachi, ltd. mc-setsu
cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. preface the h8/300l series of single-chip microcomputers has a high-speed h8/300l cpu core, with many necessary peripheral system functions on-chip. the h8/300l cpu instruction set is compatible with the h8/300 cpu. on-chip peripheral functions of the h8/3627 series include a high-precision dtmf generator for tone dialing, three types of timers, two serial communication interface channels, and an a/d converter. this manual describes the hardware of the h8/3627 series. for details on the h8/3627 series instruction set, refer to the h8/300l series programming manual. i contents section 1 overview ............................................................................................................ 1 1.1 overview.................................................................................................................... ........ 1 1.2 internal block diagram...................................................................................................... 5 1.3 pin arrangement and functions......................................................................................... 6 1.3.1 pin arrangement ................................................................................................... 6 1.3.2 pin functions ........................................................................................................ 7 section 2 cpu ..................................................................................................................... 11 2.1 overview................................................................................................................... ......... 11 2.1.1 features ................................................................................................................. 11 2.1.2 address space....................................................................................................... 12 2.1.3 register configuration.......................................................................................... 12 2.2 register descriptions ...................................................................................................... ... 13 2.2.1 general registers.................................................................................................. 13 2.2.2 control registers .................................................................................................. 13 2.2.3 initial register values .......................................................................................... 15 2.3 data formats............................................................................................................... ....... 15 2.3.1 data formats in general registers ....................................................................... 16 2.3.2 memory data formats.......................................................................................... 17 2.4 addressing modes........................................................................................................... ... 18 2.4.1 addressing modes ................................................................................................ 18 2.4.2 effective address calculation .............................................................................. 20 2.5 instruction set ............................................................................................................ ........ 24 2.5.1 data transfer instructions .................................................................................... 26 2.5.2 arithmetic operations .......................................................................................... 28 2.5.3 logic operations .................................................................................................. 29 2.5.4 shift operations .................................................................................................... 29 2.5.5 bit manipulations.................................................................................................. 31 2.5.6 branching instructions.......................................................................................... 35 2.5.7 system control instructions.................................................................................. 37 2.5.8 block data transfer instruction............................................................................ 38 2.6 basic operational timing .................................................................................................. 4 0 2.6.1 access to on-chip memory (ram, rom) ......................................................... 40 2.6.2 access to on-chip peripheral modules................................................................ 41 2.7 cpu states ................................................................................................................. ........ 42 2.7.1 overview............................................................................................................... 42 2.7.2 program execution state ...................................................................................... 44 2.7.3 program halt state................................................................................................ 44 2.7.4 exception-handling state ..................................................................................... 44 ii 2.8 memory map................................................................................................................. ..... 45 2.9 application notes .......................................................................................................... .... 46 2.9.1 notes on data access ........................................................................................... 46 2.9.2 notes on bit manipulation.................................................................................... 48 2.9.3 notes on use of the eepmov instruction ........................................................... 54 section 3 exception handling ........................................................................................ 55 3.1 overview................................................................................................................... ......... 55 3.2 reset...................................................................................................................... ............. 55 3.2.1 overview............................................................................................................... 55 3.2.2 reset sequence ..................................................................................................... 55 3.2.3 interrupt immediately after reset ......................................................................... 56 3.3 interrupts ................................................................................................................. ........... 57 3.3.1 overview............................................................................................................... 57 3.3.2 interrupt control registers ................................................................................... 59 3.3.3 external interrupts ................................................................................................ 67 3.3.4 internal interrupts.................................................................................................. 67 3.3.5 interrupt operations.............................................................................................. 68 3.3.6 interrupt response time....................................................................................... 73 3.4 application notes .......................................................................................................... .... 74 3.4.1 notes on stack area use ...................................................................................... 74 3.4.2 notes on rewriting port mode registers ............................................................. 74 section 4 clock pulse generators ................................................................................. 77 4.1 overview................................................................................................................... ......... 77 4.1.1 block diagram...................................................................................................... 77 4.1.2 system clock and subclock.................................................................................. 77 4.2 system clock generator .................................................................................................... 7 8 4.3 subclock generator......................................................................................................... ... 81 4.4 prescalers ................................................................................................................. .......... 82 4.5 note on oscillators ........................................................................................................ .... 82 section 5 power-down modes ...................................................................................... 85 5.1 overview................................................................................................................... ......... 85 5.1.1 system control registers...................................................................................... 88 5.2 sleep mode ................................................................................................................. ....... 91 5.2.1 transition to sleep mode...................................................................................... 91 5.2.2 clearing sleep mode ............................................................................................ 91 5.3 standby mode ............................................................................................................... ..... 92 5.3.1 transition to standby mode.................................................................................. 92 5.3.2 clearing standby mode ........................................................................................ 92 5.3.3 oscillator settling time after standby mode is cleared...................................... 93 5.3.4 transition to standby mode and pin states.......................................................... 94 iii 5.4 watch mode ................................................................................................................. ...... 95 5.4.1 transition to watch mode .................................................................................... 95 5.4.2 clearing watch mode ........................................................................................... 95 5.4.3 oscillator settling time after watch mode is cleared ........................................ 95 5.5 subsleep mode .............................................................................................................. ..... 96 5.5.1 transition to subsleep mode ................................................................................ 96 5.5.2 clearing subsleep mode ....................................................................................... 96 5.6 subactive mode............................................................................................................. ..... 97 5.6.1 transition to subactive mode............................................................................... 97 5.6.2 clearing subactive mode...................................................................................... 97 5.6.3 operating frequency in subactive mode ............................................................. 97 5.7 active (medium-speed) mode ........................................................................................... 98 5.7.1 transition to active (medium-speed) mode......................................................... 98 5.7.2 clearing active (medium-speed) mode................................................................ 98 5.7.3 operating frequency in active (medium-speed) mode ....................................... 98 5.8 direct transfer ............................................................................................................ ....... 99 5.8.1 overview............................................................................................................... 99 5.8.2 direct transfer time ............................................................................................ 100 section 6 rom .................................................................................................................... 103 6.1 overview................................................................................................................... ......... 103 6.1.1 block diagram...................................................................................................... 103 6.2 prom mode.................................................................................................................. .... 104 6.2.1 selection of prom mode .................................................................................... 104 6.2.2 socket adapter pin arrangement and memory map ........................................... 104 6.3 programming................................................................................................................ ...... 107 6.3.1 programming and verification ............................................................................. 108 6.3.2 programming precautions..................................................................................... 112 6.4 reliability of programmed data ........................................................................................ 113 section 7 ram .................................................................................................................... 115 7.1 overview................................................................................................................... ......... 115 7.1.1 block diagram...................................................................................................... 115 section 8 i/o ports ............................................................................................................. 117 8.1 overview................................................................................................................... ......... 117 8.2 port 1..................................................................................................................... ............. 119 8.2.1 overview............................................................................................................... 11 9 8.2.2 register configuration and description ............................................................... 119 8.2.3 pin functions ........................................................................................................ 123 8.2.4 pin states .............................................................................................................. 1 24 8.2.5 mos input pull-up............................................................................................... 125 8.3 port 2..................................................................................................................... ............. 126 iv 8.3.1 overview............................................................................................................... 12 6 8.3.2 register configuration and description ............................................................... 126 8.3.3 pin functions ........................................................................................................ 131 8.3.4 pin states .............................................................................................................. 13 3 8.3.5 mos input pull-up............................................................................................... 133 8.4 port 5..................................................................................................................... ............. 134 8.4.1 overview............................................................................................................... 13 4 8.4.2 register configuration and description ............................................................... 134 8.4.3 pin functions ........................................................................................................ 136 8.4.4 pin states .............................................................................................................. 1 37 8.4.5 mos input pull-up............................................................................................... 137 8.5 port 6..................................................................................................................... ............. 138 8.5.1 overview............................................................................................................... 13 8 8.5.2 register configuration and description ............................................................... 138 8.5.3 pin functions ........................................................................................................ 140 8.5.4 pin states .............................................................................................................. 1 40 8.5.5 mos input pull-up............................................................................................... 140 8.6 port 7..................................................................................................................... ............. 141 8.6.1 overview............................................................................................................... 14 1 8.6.2 register configuration and description ............................................................... 141 8.6.3 pin functions ........................................................................................................ 143 8.6.4 pin states .............................................................................................................. 1 43 8.7 port 8..................................................................................................................... ............. 144 8.7.1 overview............................................................................................................... 14 4 8.7.2 register configuration and description ............................................................... 144 8.7.3 pin functions ........................................................................................................ 146 8.7.4 pin states .............................................................................................................. 1 46 8.8 port a ..................................................................................................................... ............ 147 8.8.1 overview............................................................................................................... 14 7 8.8.2 register configuration and description ............................................................... 147 8.8.3 pin functions ........................................................................................................ 149 8.8.4 pin states .............................................................................................................. 1 49 8.9 port b ..................................................................................................................... ............ 150 8.9.1 overview............................................................................................................... 15 0 8.9.2 register configuration and description ............................................................... 150 section 9 timers ................................................................................................................. 151 9.1 overview................................................................................................................... ......... 151 9.2 timer a.................................................................................................................... .......... 152 9.2.1 overview............................................................................................................... 15 2 9.2.2 register descriptions............................................................................................ 153 9.2.3 timer operation.................................................................................................... 155 9.2.4 timer a operation states ..................................................................................... 156 v 9.3 timer f.................................................................................................................... ........... 157 9.3.1 overview............................................................................................................... 15 7 9.3.2 register descriptions............................................................................................ 159 9.3.3 interface with the cpu.......................................................................................... 166 9.3.4 timer operation.................................................................................................... 169 9.3.5 application notes ................................................................................................. 171 9.4 timer g.................................................................................................................... .......... 173 9.4.1 overview .............................................................................................................. 173 9.4.2 register descriptions............................................................................................ 175 9.4.3 noise canceller circuit......................................................................................... 179 9.4.4 timer operation.................................................................................................... 180 9.4.5 application notes ................................................................................................. 184 9.4.6 sample timer g application................................................................................ 188 section 10 serial communication interface ................................................................. 189 10.1 overview.................................................................................................................. .......... 189 10.2 sci1 ...................................................................................................................... ............. 189 10.2.1 overview............................................................................................................... 1 89 10.2.2 register descriptions............................................................................................ 191 10.2.3 operation .............................................................................................................. 1 95 10.2.4 interrupt sources................................................................................................... 197 10.3 sci3 ...................................................................................................................... ............. 198 10.3.1 overview............................................................................................................... 1 98 10.3.2 register descriptions............................................................................................ 200 10.3.3 operation .............................................................................................................. 2 17 10.3.4 operation in asynchronous mode........................................................................ 222 10.3.5 operation in synchronous mode .......................................................................... 230 10.3.6 multiprocessor communication function ............................................................ 238 10.3.7 interrupts .............................................................................................................. . 244 10.3.8 application notes ................................................................................................. 245 section 11 dtmf generator ............................................................................................. 249 11.1 overview.................................................................................................................. .......... 249 11.1.1 features ................................................................................................................ . 250 11.1.2 block diagram...................................................................................................... 251 11.1.3 pin configuration.................................................................................................. 252 11.1.4 register configuration.......................................................................................... 252 11.2 register descriptions ..................................................................................................... .... 253 11.2.1 dtmf control register (dtcr).......................................................................... 253 11.2.2 dtmf load register (dtlr).............................................................................. 255 11.3 operation................................................................................................................. ........... 256 11.3.1 output waveform ................................................................................................. 256 11.3.2 operation flow ..................................................................................................... 257 vi 11.4 typical use ............................................................................................................... ......... 258 11.5 application notes ......................................................................................................... ..... 258 section 12 a/d converter .................................................................................................. 259 12.1 overview.................................................................................................................. .......... 259 12.1.1 features ................................................................................................................ . 259 12.1.2 block diagram...................................................................................................... 260 12.1.3 pin configuration.................................................................................................. 260 12.1.4 register configuration.......................................................................................... 261 12.2 register descriptions ..................................................................................................... .... 261 12.2.1 a/d result register (adrr) ............................................................................... 261 12.2.2 a/d mode register (amr) .................................................................................. 262 12.2.3 a/d start register (adsr) .................................................................................. 263 12.3 operation................................................................................................................. ........... 264 12.3.1 a/d conversion operation ................................................................................... 264 12.3.2 start of a/d conversion by external trigger input ............................................. 264 12.4 interrupts ................................................................................................................ ............ 265 12.5 typical use ............................................................................................................... ......... 265 12.6 application notes ......................................................................................................... ..... 268 section 13 power supply circuit ..................................................................................... 269 13.1 overview.................................................................................................................. .......... 269 13.2 internal power supply step-down circuit formats .......................................................... 269 section 14 electrical characteristics .............................................................................. 271 14.1 absolute maximum ratings .............................................................................................. 271 14.2 electrical characteristics................................................................................................ .... 272 14.2.1 power supply voltage and operating range ....................................................... 272 14.2.2 dc characteristics ................................................................................................ 274 14.2.3 ac characteristics ................................................................................................ 279 14.2.4 a/d converter characteristics.............................................................................. 282 14.2.5 dtmf characteristics .......................................................................................... 283 14.3 operation timing .......................................................................................................... ..... 284 14.4 output load circuits...................................................................................................... .... 287 appendix a cpu instruction set .................................................................................... 289 a.1 instructions............................................................................................................... .......... 289 a.2 operation code map......................................................................................................... . 297 a.3 number of execution states .............................................................................................. 299 appendix b on-chip registers ...................................................................................... 306 b.1 i/o registers (1).......................................................................................................... ....... 306 b.2 i/o registers (2).......................................................................................................... ....... 310 vii appendix c i/o port block diagrams .......................................................................... 344 c.1 port 1 block diagrams ...................................................................................................... . 344 c.2 port 2 block diagrams ...................................................................................................... . 351 c.3 port 5 block diagram ....................................................................................................... . 359 c.4 port 6 block diagram ....................................................................................................... . 360 c.5 port 7 block diagram ....................................................................................................... . 361 c.6 port 8 block diagram ....................................................................................................... . 362 c.7 port a block diagram....................................................................................................... . 363 c.8 port b block diagram....................................................................................................... . 363 appendix d port states in the different processing states .................................... 364 appendix e product line-up .......................................................................................... 365 appendix f package dimensions .................................................................................. 366 1 section 1 overview 1.1 overview the h8/300l series is a series of single-chip microcomputers (mcu: microcomputer unit), built around the high-speed h8/300l cpu and equipped with peripheral system functions on-chip. within the h8/300l series, the h8/3627 series of single-chip microcomputers features a high- precision dtmf generator for tone dialing. other on-chip peripheral functions include three types of timers, two serial communication interface channels, and an a/d converter. the h8/3627 series includes six models, the h8/3627, h8/3626, h8/3625, h8/3624, h8/3623, and h8/3622, with different amounts of on-chip memory: the h8/3627 has 60 kbytes of rom and 2 kbytes of ram; the h8/3626 has 48 kbytes of rom and 2 kbytes of ram; the h8/3625 has 40 kbytes of rom and 2 kbytes of ram; the h8/3624s has 32 kbytes of rom and 1 kbyte of ram; the h8/3623s has 24 kbytes of rom and 1 kbyte of ram; and the h8/3622s has 16 kbytes of rom and 1 kbyte of ram. in addition, thanks to the improvement of the power supply circuit, low power consumption and low radiation noise have been realized. the h8/3627 has a ztat ? * version with user-programmable on-chip prom. table 1.1 summarizes the features of the h8/3627 series. note: * ztat tm is a trademark of hitachi, ltd. 2 table 1.1 features item description cpu high-speed h8/300l cpu general-register architecture ? general registers: sixteen 8-bit registers (can be used as eight 16-bit registers) operating speed ? max. operating speed: 5 mhz ? add/subtract: 0.4 m s (operating at ? 5 mhz) ? multiply/divide: 2.8 m s (operating at ? 5 mhz) ? can run on 32.768 khz subclock instruction set compatible with h8/300 cpu ? instruction length of 2 bytes or 4 bytes ? basic arithmetic operations between registers ? mov instruction for data transfer between memory and registers instruction features ? multiply (8 bits 8 bits) ? divide (16 bits ? 8 bits) ? bit accumulator ? register-indirect designation of bit position interrupts 29 interrupt sources 13 external interrupt sources: irq 4 to irq 0 , wkp 7 to wkp 0 16 internal interrupt sources clock pulse generators two on-chip clock pulse generators system clock pulse generator: 1 mhz to 10 mhz subclock pulse generator: 32.768 khz power-down modes six power-down modes sleep mode standby mode watch mode subsleep mode subactive mode active (medium-speed) mode 3 table 1.1 features (cont) item description memory large on-chip memory ? h8/3627: 60-kbyte rom, 2-kbyte ram ? h8/3626: 48-kbyte rom, 2-kbyte ram ? h8/3625: 40-kbyte rom, 2-kbyte ram ? h8/3624s: 32-kbyte rom, 1-kbyte ram ? h8/3623s: 24-kbyte rom, 1-kbyte ram ? h8/3622s: 16-kbyte rom, 1-kbyte ram i/o ports 53 i/o ports ? i/o pins: 50 ? input pins: 3 timers 3 on-chip timers ? timer a: 8-bit timer with built-in interval/watch clock time base function ? count-up timer with selection of eight internal clock signals divided from the system clock (? * and four clock signals divided from the watch clock ( w ) * ? timer f: 16-bit timer with built-in output compare function ? can be used as two independent 8-bit timers. ? count-up timer with selection of four internal clock signals or event input from external pin ? compare-match function with toggle output ? timer g: 8-bit timer with built-in input capture/interval functions ? count-up timer with selection of four internal clock signals ? input capture function with built-in noise canceller circuit serial communication interface two serial communication interface channels on chip ? sci1: synchronous serial interface ? choice of 8-bit or 16-bit data transfer ? sci3: 8-bit synchronous or asynchronous serial interface ? built-in function for multiprocessor communication note: * ?and w are defined in section 4, clock pulse generators. 4 table 1.1 features (cont) item description a/d converter 8-bit successive-approximations a/d converter using a resistance ladder ? 2-channel analog input port ? conversion time: 31/? 62/?or 124/?per channel dtmf generator built-in tone dialer supporting osc clock frequencies from 1.2 mhz to 10 mhz in 400-khz steps product lineup product code mask rom version ztat version package rom/ram size hd6433627h hd6473627h 64-pin qfp (fp-64a) rom: 60 kbytes ram: 2 kbytes hd6433627fp hd6473627fp 64-pin lqfp (fp-64e) hd6433626h 64-pin qfp (fp-64a) rom: 48 kbytes ram: 2 kbytes hd6433626fp 64-pin lqfp (fp-64e) hd6433625h 64-pin qfp (fp-64a) rom: 40 kbytes ram: 2 kbytes hd6433625fp 64-pin lqfp (fp-64e) hd6433624sh 64-pin qfp (fp-64a) rom: 32 kbytes ram: 1 kbyte hd6433624sfp 64-pin lqfp (fp-64e) hd6433623sh 64-pin qfp (fp-64a) rom: 24 kbytes ram: 1 kbyte hd6433623sfp 64-pin lqfp (fp-64e) HD6433622Sh 64-pin qfp (fp-64a) rom: 16 kbytes ram: 1 kbyte HD6433622Sfp 64-pin lqfp (fp-64e) 5 1.2 internal block diagram figure 1.1 shows a block diagram of the h8/3627 series. v ss v cc cv cc osc 2 osc 1 x 1 x 2 res test p8 7 p8 6 p8 5 p8 4 p8 3 p8 2 p8 1 p8 0 p7 7 p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p7 0 pa 3 pa 2 pa 1 p1 0 /tmow p1 1 /tmofl p1 2 /tmofh p1 3 /tmig p1 4 p1 5 / irq1 p1 6 / irq2 p1 7 / irq3 /tmif p2 0 / irq4 / adtrg p2 1 /sck1 p2 2 /si1 p2 3 /so1 p2 4 /sck3 p2 5 /rxd p2 6 /txd p2 7 / irq0 p5 0 / wkp0 p5 1 / wkp1 p5 2 / wkp2 p5 3 / wkp3 p5 4 / wkp4 p5 5 / wkp5 p5 6 / wkp6 p5 7 / wkp7 p6 0 p6 1 p6 2 p6 3 p6 4 p6 5 p6 6 p6 7 pb 6 /an 6 pb 7 /an 7 sci3 dtmf sci1 vt ref toned data bus (lower) system clock pulse generator subclock pulse generator address bus data bus (upper) rom 16 k/24 k/ 32 k/40 k/ 48 k/60 k bytes ram (1 k/2 kbytes) timer a timer f timer g a/d converter port a port 8 port 7 port b port 6 port 5 port 2 port 1 cpu (8-bit) figure 1.1 block diagram 6 1.3 pin arrangement and functions 1.3.1 pin arrangement the h8/3627 series pin arrangement is shown in figure 1.2. p7 4 p7 3 p7 2 p7 1 p7 0 p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 p5 7 / wkp 7 p5 6 / wkp 6 p5 5 / wkp 5 x 1 x 2 v ss osc 2 osc 1 test v cc res p2 0 / irq4 / adtrg p2 1 /sck 1 p2 2 /si 1 p2 3 /so 1 p2 4 /sck 3 p2 5 /rxd p2 6 /txd p2 7 / irq0 p7 5 p7 6 p7 7 p8 0 p8 1 p8 2 p8 3 p8 4 p8 5 p8 6 p8 7 toned vt ref pb 7 /an 7 pb 6 /an 6 cv cc p5 4 / wkp 4 p5 3 / wkp 3 p5 2 / wkp 2 p5 1 / wkp 1 p5 0 / wkp 0 pa 1 pa 2 pa 3 p1 0 /tmow p1 1 /tmofl p1 2 /tmofh p1 3 /tmig p1 4 p1 5 / irq 1 p1 6 / irq 2 p1 7 / irq 3 /tmif 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 12345678910111213141516 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 figure 1.2 pin arrangement (fp-64a, fp-64e: top view) 7 1.3.2 pin functions table 1.2 outlines the pin functions. table 1.2 pin functions pin no. type symbol fp-64a fp-64e i/o name and functions power source pins v cc 7 input power supply: all v cc pins should be connected to the system power supply (+5 v) v ss 3 input ground: all v ss pins should be connected to the system power supply (0 v) cv cc 64 input connected a 0.1 m f stabilization capacitor between the cv cc pin and ground. vt ref 61 input dtmf generator reference level: this is a power supply pin for the reference level for dtmf. clock pins osc 1 5 input system clock: these pins connect to a crystal or ceramic oscillator, or can be used to input external osc 2 4 output an clock. see section 4, clock pulse generators, for a typical connection diagram. x 1 1 input subclock: these pins connect to a 32.768-khz crystal oscillator. see section 4, clock pulse x 2 2 output generators, for a typical connection diagram. system res 8 input reset: when this pin is driven low, the chip is reset control test 6 input test: this is a test pin, not for use in applica-tion systems. it should be connected to v ss . interrupt pins irq 0 irq 1 irq 2 irq 3 irq 4 16 19 18 17 9 input external interrupt request 0 to 4: these are input pins for external interrupts for which there is a choice between rising and falling edge sensing wkp 7 to wkp 0 35 to 28 input wakeup interrupt request 0 to 7: these are input pins for external interrupts that are detected at the falling edge 8 table 1.2 pin functions (cont) pin no. type symbol fp-64a fp-64e i/o name and functions timer pins tmow 24 output clock output: this is an output pin for wave-forms generated by the timer a output circuit tmif 17 input timer f event counter input: this is an event input pin for input to the timer f counter tmofl 23 output timer fl output: this is an output pin for waveforms generated by the timer fl output compare function tmofh 22 output timer fh output: this is an output pin for waveforms generated by the timer fh output compare function tmig 21 input timer g capture input: this is an input pin for the timer g input capture function i/o ports pb 7 , pb 6 62 to 63 input port b: this is a 2-bit input port pa 3 to pa 1 25 to 27 i/o port a: this is a 3-bit i/o port. input or output can be designated for each bit by means of port control register a (pcra). p1 7 to p1 0 17 to 24 i/o port 1: this is an 8-bit i/o port. input or output can be designated for each bit be means of port control register 1 (pcr1). p2 7 16 input port 2 (bit 7): this is a 1-bit input port. p2 6 to p2 0 15 to 9 i/o port 2 (bits 6 to 0): this is a 7-bit i/o port. input or output can be designated for each bit by means of port control register 2 (pcr2). p5 7 to p5 0 35 to 28 i/o port 5: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 5 (pcr5). p6 7 to p6 0 43 to 36 i/o port 6: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 6 (pcr6). p7 7 to p7 0 51 to 44 i/o port 7: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 7 (pcr7). p8 7 to p8 0 59 to 52 i/o port 8: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 8 (pcr8). 9 table 1.2 pin functions (cont) pin no. type symbol fp-64a fp-64e i/o name and functions serial com- munication si 1 11 input sci1 receive data input: this is the sci1 data input pin interface (sci) so 1 12 output sci1 send data output: this is the sci1 data output pin sck 1 10 i/o sci1 clock i/o : this is the sci1 clock i/o pin rxd 14 input sci3 receive data input: this is the sci3 data input pin txd 15 output sci3 send data output: this is the sci3 data output pin sck 3 13 i/o sci3 clock i/o: this is the sci3 clock i/o pin a/d c onv er ter an 7 , an 6 62, 63 input analog input channels 6, 7: these are analog data input channels to the a/d converter adtrg 9 input a/d converter trigger input: this is the external trigger input pin to the a/d converter dtmf generator toned 60 output dtmf signal: this is the output pin for the dtmf signal 10 11 section 2 cpu 2.1 overview the h8/300l cpu has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. its concise, optimized instruction set is designed for high-speed operation. 2.1.1 features features of the h8/300l cpu are listed below. general-register architecture sixteen 8-bit general registers, also usable as eight 16-bit general registers instruction set with 55 basic instructions, including: ? multiply and divide instructions ? powerful bit-manipulation instructions eight addressing modes ? register direct ? register indirect ? register indirect with displacement ? register indirect with post-increment or pre-decrement ? absolute address ? immediate ? program-counter relative ? memory indirect 64-kbyte address space high-speed operation ? all frequently used instructions are executed in two to four states ? high-speed arithmetic and logic operations 8- or 16-bit register-register add or subtract: 0.4 m s* 8 8-bit multiply: 2.8 m s* 16 ? 8-bit divide: 2.8 m s* low-power operation modes sleep instruction for transition to low-power operation note: * these values are at ? = 5 mhz. 12 2.1.2 address space the h8/300l cpu supports an address space of up to 64 kbytes for storing program code and data. see 2.8, memory map, for details of the memory map. 2.1.3 register configuration figure 2.1 shows the register structure of the h8/300l cpu. there are two groups of registers: the general registers and control registers. 7070 15 0 pc r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l (sp) sp: stack pointer pc: program counter ccr: condition code register carry flag overflow flag zero flag negative flag half-carry flag interrupt mask bit user bit user bit ccr i u h u n z v c general registers (rn) control registers (cr) 753210 64 figure 2.1 cpu registers 13 2.2 register descriptions 2.2.1 general registers all the general registers have the same functions, and can be used as both data registers and address registers. when used as data registers, they can be accessed as 16-bit registers (r0 to r7), or the high bytes (r0h to r7h) and low bytes (r0l to r7l) can be accessed separately as 8-bit registers. when used as address registers, the general registers are accessed as 16-bit registers (r0 to r7). r7 also functions as the stack pointer (sp), used implicitly by hardware in exception handling and subroutine calls. when it functions as the stack pointer, as indicated in figure 2.2, sp (r7) points to the top of the stack. lower address side [h'0000] upper address side [h'ffff] unused area stack area sp (r7) figure 2.2 stack pointer 2.2.2 control registers the cpu control registers include a 16-bit program counter (pc) and an 8-bit condition code register (ccr). (1) program counter (pc): this 16-bit register indicates the address of the next instruction the cpu will execute. all instructions are fetched 16 bits (1 word) at a time, so the least significant bit of the pc is ignored (always regarded as 0). 14 (2) condition code register (ccr): this 8-bit register contains internal status information, including the interrupt mask bit (i) and half-carry (h), negative (n), zero (z), overflow (v), and carry (c) flags. these bits can be read and written by software (using the ldc, stc, andc, orc, and xorc instructions). the n, z, v, and c flags are used as branching conditions for conditional branching (bcc) instructions. bit 7?nterrupt mask bit (i): when this bit is set to 1, interrupts are masked. this bit is set to 1 automatically at the start of exception handling. the interrupt mask bit may be read and written by software. for further details, see 3.3, interrupts. bit 6?ser bit (u): can be used freely by the user. bit 5?alf-carry flag (h): when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and is cleared to 0 otherwise. the h flag is used implicitly by the daa and das instructions. when the add.w, sub.w, or cmp.w instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 11, and is cleared to 0 otherwise. bit 4?ser bit (u): can be used freely by the user. bit 3?egative flag (n): indicates the most significant bit (sign bit) of the result of an instruction. bit 2?ero flag (z): set to 1 to indicate a zero result, and cleared to 0 to indicate a non-zero result. bit 1?verflow flag (v): set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. bit 0?arry flag (c): set to 1 when a carry occurs, and cleared to 0 otherwise. used by: add instructions, to indicate a carry subtract instructions, to indicate a borrow shift/rotate carry the carry flag is also used as a bit accumulator by bit manipulation instructions. some instructions leave some or all of the flag bits unchanged. refer to the h8/300l series programming manual for the action of each instruction on the flag bits. 15 2.2.3 initial register values when the cpu is reset, the program counter (pc) is initialized to the value stored at address h'0000 in the vector table, and the i bit in the ccr is set to 1. the other ccr bits and the general registers are not initialized. in particular, the stack pointer (r7) is not initialized. r7 initialization should therefore be carried out immediately after a reset. 2.3 data formats the h8/300l cpu can process 1-bit data, 4-bit (bcd) data, 8-bit (byte) data, and 16-bit (word) data. bit manipulation instructions operate on 1-bit data specified as bit n in a byte operand (n??, 1, 2, ..., 7). all arithmetic and logic instructions except adds and subs can operate on byte data. the mov.w, add.w, sub.w, cmp.w, adds, subs, mulxu (8 bits 8 bits), and divxu (16 bits ? 8 bits) instructions operate on word data. the daa and das instructions perform decimal arithmetic adjustments on byte data in two-digit 4-bit bcd form. 16 2.3.1 data formats in general registers general register data formats are shown in figure 2.3. 76543210 don? care data type register no. data format 70 1-bit data rnh 76543210 don? care 70 1-bit data rnl msb lsb don? care 70 byte data rnh byte data rnl word data rn 4-bit bcd data rnh 4-bit bcd data rnl legend: rnh: rnl: msb: lsb: upper byte of general register lower byte of general register most significant bit least significant bit msb lsb don? care 70 msb lsb 15 0 upper digit lower digit don? care 70 3 4 don? care upper digit lower digit 70 3 4 figure 2.3 register data formats 17 2.3.2 memory data formats figure 2.4 indicates the data formats in memory. for access by the h8/300l cpu, word data stored in memory must always begin at an even address. in word access the least significant bit of the address is regarded as 0. if an odd address is specified, the access is performed at the preceding even address. this rule affects the mov.w instruction, and also applies to instruction fetching. data format 76543210 address data type 70 address n msb lsb msb lsb upper 8 bits lower 8 bits msb lsb ccr ccr * msb lsb msb lsb address n even address odd address even address odd address even address odd address 1-bit data byte data word data byte data (ccr) on stack word data on stack ccr: condition code register note: ignored on return * figure 2.4 memory data formats when the stack is accessed using r7 as an address register, word access should always be performed. when the ccr is pushed on the stack, two identical copies of the ccr are pushed to make a complete word. when they are restored, the lower byte is ignored. 18 2.4 addressing modes 2.4.1 addressing modes the h8/300l cpu supports the eight addressing modes listed in table 2.1. each instruction uses a subset of these addressing modes. table 2.1 addressing modes no. address modes symbol 1 register direct rn 2 register indirect @rn 3 register indirect with displacement @(d:16, rn) 4 register indirect with post-increment register indirect with pre-decrement @rn+ @?n 5 absolute address @aa:8 or @aa:16 6 immediate #xx:8 or #xx:16 7 program-counter relative @(d:8, pc) 8 memory indirect @@aa:8 1. register direct?n: the register field of the instruction specifies an 8- or 16-bit general register containing the operand. only the mov.w, add.w, sub.w, cmp.w, adds, subs, mulxu (8 bits 8 bits), and divxu (16 bits ? 8 bits) instructions have 16-bit operands. 2. register indirect?@rn: the register field of the instruction specifies a 16-bit general register containing the address of the operand in memory. 3. register indirect with displacement?@(d:16, rn): the instruction has a second word (bytes 3 and 4) containing a displacement which is added to the contents of the specified general register to obtain the operand address in memory. this mode is used only in mov instructions. for the mov.w instruction, the resulting address must be even. 19 4. register indirect with post-increment or pre-decrement?rn+ or @?n: register indirect with post-increment?@rn+ the @rn+ mode is used with mov instructions that load registers from memory. the register field of the instruction specifies a 16-bit general register containing the address of the operand. after the operand is accessed, the register is incremented by 1 for mov.b or 2 for mov.w. for mov.w, the original contents of the 16-bit general register must be even. register indirect with pre-decrement?@ern the @ern mode is used with mov instructions that store register contents to memory. the register field of the instruction specifies a 16-bit general register which is decremented by 1 or 2 to obtain the address of the operand in memory. the register retains the decremented value. the size of the decrement is 1 for mov.b or 2 for mov.w. for mov.w, the original contents of the register must be even. 5. absolute address?@aa:8 or @aa:16: the instruction specifies the absolute address of the operand in memory. the absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). the mov.b and bit manipulation instructions can use 8-bit absolute addresses. the mov.b, mov.w, jmp, and jsr instructions can use 16-bit absolute addresses. for an 8-bit absolute address, the upper 8 bits are assumed to be 1 (h'ff). the address range is h'ff00 to h'ffff (65280 to 65535). 6. immediate?#xx:8 or #xx:16: the instruction contains an 8-bit operand (#xx:8) in its second byte, or a 16-bit operand (#xx:16) in its third and fourth bytes. only mov.w instructions can contain 16-bit immediate values. the adds and subs instructions implicitly contain the value 1 or 2 as immediate data. some bit manipulation instructions contain 3-bit immediate data in the second or fourth byte of the instruction, specifying a bit number. 7. program-counter relative?@(d:8, pc): this mode is used in the bcc and bsr instructions. an 8-bit displacement in byte 2 of the instruction code is sign-extended to 16 bits and added to the program counter contents to generate a branch destination address. the possible branching range is e126 to +128 bytes (e63 to +64 words) from the current address. the result of the addition should be an even number. 20 8. memory indirect?@aa:8: this mode can be used by the jmp and jsr instructions. the second byte of the instruction code specifies an 8-bit absolute address. the word located at this address contains the branch destination address. the upper 8 bits of the absolute address are assumed to be 0 (h'00), so the address range is h'0000 to h'00ff (0 to 255). note that with the h8/300l series, the lower end of the address area is also used as a vector area. see 3.3, interrupts, for details on the vector area. if an odd address is specified as a branch destination or as the operand address of a mov.w instruction, the least significant bit is regarded as 0, causing word access to be performed at the address preceding the specified address. see 2.3.2, memory data formats, for further information. 2.4.2 effective address calculation table 2.2 shows how effective addresses are calculated in each of the addressing modes. arithmetic and logic instructions use register direct addressing (1). the add.b, addx, subx, cmp.b, and, or, and xor instructions can also use immediate addressing (6). data transfer instructions can use all addressing modes except program-counter relative (7) and memory indirect (8). bit manipulation instructions use register direct (1), register indirect (2), or 8-bit absolute addressing (5) to specify a byte operand, and 3-bit immediate addressing (6) to specify a bit position in that byte. the bset, bclr, bnot, and btst instructions can also use register direct addressing (1) to specify the bit position. 21 table 2.2 effective address calculation no. addressing mode and instruction format effective address calculation method effective address (ea) 1 register direct, rn operand is contents of registers indicated by rm/rn op rm rn 87 3 40 15 rm 30 rn 30 2 op rm 76 3 40 15 register indirect, @rn contents (16 bits) of register indicated by rm 0 15 0 15 3 register indirect with displacement, @(d:16, rn) op rm 76 3 40 15 disp 0 15 disp 0 15 contents (16 bits) of register indicated by rm 4 op rm 76 3 40 15 register indirect with post-increment, @rn+ op rm 76 3 40 15 register indirect with pre-decrement, @?n incremented or decremented by 1 if operand is byte size, and by 2 if word size 0 15 1 or 2 0 15 0 15 1 or 2 0 15 contents (16 bits) of register indicated by rm contents (16 bits) of register indicated by rm 22 table 2.2 effective address calculation (cont) no. addressing mode and instruction format effective address calculation method effective address (ea) 5 absolute address @aa:8 @aa:16 op 87 0 15 0 15 abs h'ff 87 0 15 0 15 abs op 6 op 0 15 imm #xx:16 op 87 0 15 imm immediate #xx:8 operand is 1- or 2-byte immediate data 7 op disp 70 15 program-counter relative @(d:8, pc) pc contents 0 15 0 15 8 sign extension disp 23 table 2.2 effective address calculation (cont) no. addressing mode and instruction format effective address calculation method effective address (ea) 8 memory indirect, @@aa:8 op 87 0 15 memory contents (16 bits) 0 15 abs h'00 87 0 15 abs legend: rm, rn: register field op: operation field disp: displacement imm: immediate data abs: absolute address 24 2.5 instruction set the h8/300l series can use a total of 55 instructions, which are grouped by function in table 2.3. table 2.3 instruction set function instructions number data transfer mov, push *1 , pop *1 1 arithmetic operations add, sub, addx, subx, inc, dec, adds, subs, daa, das, mulxu, divxu, cmp, neg 14 logic operations and, or, xor, not 4 shift shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr 8 bit manipulation bset, bclr, bnot, btst, band, biand, bor, bior, bxor, bixor, bld, bild, bst, bist 14 branch bcc *2 , jmp, bsr, jsr, rts 5 system control rte, sleep, ldc, stc, andc, orc, xorc, nop 8 block data transfer eepmov 1 total: 55 notes: 1. push rn is equivalent to mov.w rn, @?p. pop rn is equivalent to mov.w @sp+, rn. the machine language is also the same. 2. bcc is a conditional branch instruction in which cc represents a condition code. the following sections give a concise summary of the instructions in each category, and indicate the bit patterns of their object code. the notation used is defined next. the functions of the instructions are shown in tables 2.4 to 2.11. the meaning of the operation symbols used in the tables is as follows. 25 notation rd general register (destination) rs general register (source) rn general register (ead), 26 2.5.1 data transfer instructions table 2.4 describes the data transfer instructions. figure 2.5 shows their object code formats. table 2.4 data transfer instructions instruction size * function mov b/w (eas) ? rd, rs ? (ead) moves data between two general registers or between a general register and memory, or moves immediate data to a general register. the rn, @rn, @(d:16, rn), @aa:16, #xx:16, @?n, and @rn+ addressing modes are available for byte or word data. the @aa:8 addressing mode is available for byte data only. the @?7 and @r7+ modes require word operands. do not specify byte size for these two modes. pop w @sp+ ? rn pops a 16-bit general register from the stack. equivalent to mov.w @sp+, rn. push w rn ? @?p pushes a 16-bit general register onto the stack. equivalent to mov.w rn, @?p. note: * size: operand size b: byte w: word certain precautions are required in data access. see 2.9.1, notes on data access, for details. 27 15 0 87 op rm rn mov rm ? rn 15 0 87 op rm rn @rm ?? rn 15 0 87 op rm rn @(d:16, rm) ?? rn disp 15 0 87 op rm rn @rm+ ? rn, or rn ? @erm 15 0 87 op rn abs @aa:8 ?? rn 15 0 87 op rn @aa:16 ?? rn abs 15 0 87 op rn imm #xx:8 ? rn 15 0 87 op rn #xx:16 ? rn imm 15 0 87 op rn push, pop legend: op: rm, rn: disp: abs: imm: operation field register field displacement absolute address immediate data @sp+ rn, or rn @esp ? ? 111 figure 2.5 data transfer instruction codes 28 2.5.2 arithmetic operations table 2.5 describes the arithmetic instructions. table 2.5 arithmetic instructions instruction size * function add sub b/w rd rs ? rd, rd + #imm ? rd performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. immediate data cannot be subtracted from data in a general register. word data can be added or subtracted only when both words are in general registers. addx subx b rd rs c ? rd, rd #imm c ? rd performs addition or subtraction with carry or borrow on byte data in two general registers, or addition or subtraction on immediate data and data in a general register. inc dec b rd 1 ? rd increments or decrements a general register adds subs w rd 1 ? rd, rd 2 ? rd adds or subtracts immediate data to or from data in a general register. the immediate data must be 1 or 2. daa das b rd decimal adjust ? rd decimal-adjusts (adjusts to packed 4-bit bcd) an addition or subtraction result in a general register by referring to the ccr mulxu b rd rs ? rd performs 8-bit 8-bit unsigned multiplication on data in two general registers, providing a 16-bit result divxu b rd ? rs ? rd performs 16-bit ? 8-bit unsigned division on data in two general registers, providing an 8-bit quotient and 8-bit remainder cmp b/w rd ?rs, rd ?#imm compares data in a general register with data in another general register or with immediate data, and the result is stored in the ccr. word data can be compared only between two general registers. neg b 0 ?rd ? rd obtains the two? complement (arithmetic complement) of data in a general register note: * size: operand size b: byte w: word 29 2.5.3 logic operations table 2.6 describes the four instructions that perform logic operations. table 2.6 logic operation instructions instruction size * function and b rd rs ? rd, rd #imm ? rd performs a logical and operation on a general register and another general register or immediate data or b rd rs ? rd, rd #imm ? rd performs a logical or operation on a general register and another general register or immediate data xor b rd ? rs ? rd, rd ? #imm ? rd performs a logical exclusive or operation on a general register and another general register or immediate data not b ~ rd ? rd obtains the one? complement (logical complement) of general register contents note: * size: operand size b: byte 2.5.4 shift operations table 2.7 describes the eight shift instructions. table 2.7 shift instructions instruction size * function shal shar b rd shift ? rd performs an arithmetic shift operation on general register contents shll shlr b rd shift ? rd performs a logical shift operation on general register contents rotl rotr b rd rotate ? rd rotates general register contents rotxl rotxr b rd rotate through carry ? rd rotates general register contents through the c (carry) bit note: * size: operand size b: byte 30 figure 2.6 shows the instruction code format of arithmetic, logic, and shift instructions. 15 0 87 op rm rn add, sub, cmp, addx, subx (rm) legend: op: rm, rn: imm: operation field register field immediate data 15 0 87 op rn adds, subs, inc, dec, daa, das, neg, not 15 0 87 op rn mulxu, divxu rm 15 0 87 rn imm add, addx, subx, cmp (#xx:8) op 15 0 87 op rn and, or, xor (rm) rm 15 0 87 rn imm and, or, xor (#xx:8) op 15 0 87 rn shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr op figure 2.6 arithmetic, logic, and shift instruction codes 31 2.5.5 bit manipulations table 2.8 describes the bit-manipulation instructions. figure 2.7 shows their object code formats. table 2.8 bit-manipulation instructions instruction size * function bset b 1 ? ( 32 table 2.8 bit-manipulation instructions (cont) instruction size * function bxor b c ? ( 33 15 0 87 op imm rn operand: bit no.: legend: op: rm, rn: abs: imm: operation field register field absolute address immediate data 15 0 87 op rn bset, bclr, bnot, btst register direct (rn) immediate (#xx:3) operand: bit no.: register direct (rn) register direct (rm) rm 15 0 87 op 0 operand: bit no.: register indirect (@rn) immediate (#xx:3) rn 0 0 0 0 0 0 0 imm 15 0 87 op 0 operand: bit no.: register indirect (@rn) register direct (rm) rn 0 0 0 0 0 0 0 rm op 15 0 87 op operand: bit no.: absolute (@aa:8) immediate (#xx:3) abs 0000 imm op op 15 0 87 op operand: bit no.: absolute (@aa:8) register direct (rm) abs 0000 rm op 15 0 87 op imm rn operand: bit no.: register direct (rn) immediate (#xx:3) band, bor, bxor, bld, bst 15 0 87 op 0 operand: bit no.: register indirect (@rn) immediate (#xx:3) rn 0 0 0 0 0 0 0 imm op 15 0 87 op operand: bit no.: absolute (@aa:8) immediate (#xx:3) abs 0000 imm op figure 2.7 bit manipulation instruction codes 34 legend: op: rm, rn: abs: imm: operation field register field absolute address immediate data 15 0 87 op imm rn operand: bit no.: register direct (rn) immediate (#xx:3) biand, bior, bixor, bild, bist 15 0 87 op 0 operand: bit no.: register indirect (@rn) immediate (#xx:3) rn 0 0 0 0 0 0 0 imm op 15 0 87 op operand: bit no.: absolute (@aa:8) immediate (#xx:3) abs 0000 imm op figure 2.7 bit manipulation instruction codes (cont) 35 2.5.6 branching instructions table 2.9 describes the branching instructions. figure 2.8 shows their object code formats. table 2.9 branching instructions instruction size function bcc branches to the designated address if the specified condition is true. the branching conditions are given below. mnemonic description condition bra (bt) always (true) always brn (bf) never (false) never bhi high c z = 0 bls low or same c z = 1 bcc (bhs) carry clear (high or same) c = 0 bcs (blo) carry set (low) c = 1 bne not equal z = 0 beq equal z = 1 bvc overflow clear v = 0 bvs overflow set v = 1 bpl plus n = 0 bmi minus n = 1 bge greater or equal n ? v = 0 blt less than n ? v = 1 bgt greater than z (n ? v) = 0 ble less or equal z (n ? v) = 1 jmp branches unconditionally to a specified address bsr branches to a subroutine at a specified address jsr branches to a subroutine at a specified address rts returns from a subroutine 36 legend: op: cc: rm: disp: abs: operation field condition field register field displacement absolute address 15 0 87 op cc disp bcc 15 0 87 op rm 0 jmp (@rm) 000 15 0 87 op jmp (@aa:16) abs 15 0 87 op abs jmp (@@aa:8) 15 0 87 op disp bsr 15 0 87 op rm 0 jsr (@rm) 000 15 0 87 op jsr (@aa:16) abs 15 0 87 op abs jsr (@@aa:8) 15 0 87 op rts figure 2.8 branching instruction codes 37 2.5.7 system control instructions table 2.10 describes the system control instructions. figure 2.9 shows their object code formats. table 2.10 system control instructions instruction size * function rte returns from an exception-handling routine sleep causes a transition from active mode to a power-down mode. see section 5, power-down modes, for details ldc b rs ? ccr, #imm ? ccr moves immediate data or general register contents to the condition code register stc b ccr ? rd copies the condition code register to a specified general register andc b ccr #imm ? ccr logically ands the condition code register with immediate data orc b ccr #imm ? ccr logically ors the condition code register with immediate data xorc b ccr ? #imm ? ccr logically exclusive-ors the condition code register with immediate data nop pc + 2 ? pc only increments the program counter note: * size: operand size b: byte 38 legend: op: rn: imm: operation field register field immediate data 15 0 87 op rte, sleep, nop 15 0 87 op rn ldc, stc (rn) 15 0 87 op imm andc, orc, xorc, ldc (#xx:8) figure 2.9 system control instruction codes 2.5.8 block data transfer instruction table 2.11 describes the block data transfer instruction. figure 2.10 shows its object code format. table 2.11 block data transfer instruction instruction size function eepmov if r4l 1 0 then repeat @r5+ ? @r6+, r4l ?1 ? r4l until r4l = 0 else next; block transfer instruction. transfers the number of bytes specified by r4l, from locations starting at the address specified by r5, to locations starting at the address specified by r6. on completion of the transfer, the next instruction is executed. certain precautions are required in using the eepmov instruction. see 2.9.3, notes on use of the eepmov instruction, for details. 39 legend: op: operation field 15 0 87 op op figure 2.10 block data transfer instruction code 40 2.6 basic operational timing cpu operation is synchronized by a system clock (? or a subclock ( sub ). for details on these clock signals see section 4, clock pulse generators. the period from a rising edge of ?or sub to the next rising edge is called one state. a bus cycle consists of two states or three states. the cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 access to on-chip memory (ram, rom) acess to on-chip memory takes place in two states. the data bus width is 16 bits, allowing access in byte or word size. figure 2.11 shows the on-chip memory access cycle. t 1 state bus cycle t 2 state internal address bus internal read signal internal data bus (read access) internal write signal read data address write data internal data bus (write access) sub ?or figure 2.11 on-chip memory access cycle 41 2.6.2 access to on-chip peripheral modules on-chip peripheral modules are accessed in two states or three states. the data bus width is 8 bits, so access is by byte size only. this means that for accessing word data, two instructions must be used. two-state access to on-chip peripheral modules figure 2.12 shows operation timings for accessing on-chip peripheral modules in 2 states. t 1 state bus cycle t 2 state ?or internal address bus internal read signal internal data bus (read access) internal write signal read data address write data internal data bus (write access) sub figure 2.12 on-chip peripheral module access cycle (2-state access) three-state access to on-chip peripheral modules figure 2.13 shows operation timings for accessing on-chip peripheral modules in 3 states. 42 t 1 state bus cycle internal address bus internal read signal internal data bus (read access) internal write signal read data address internal data bus (write access) t 2 state t 3 state write data sub ?or figure 2.13 on-chip peripheral module access cycle (3-state access) 2.7 cpu states 2.7.1 overview there are four cpu states: the reset state, program execution state, program halt state, and exception-handling state. the program execution state includes active (high-speed or medium- speed) mode and subactive mode. in the program halt state there are a sleep mode, standby mode, watch mode, and sub-sleep mode. these states are shown in figure 2.14. figure 2.15 shows the state transitions. 43 cpu state reset state program execution state program halt state exception- handling state active (high speed) mode active (medium speed) mode subactive mode sleep mode standby mode watch mode subsleep mode low-power modes the cpu executes successive program instructions at high speed, synchronized by the system clock the cpu executes successive program instructions at reduced speed, synchronized by the system clock the cpu executes successive program instructions at reduced speed, synchronized by the subclock a state in which some or all of the chip functions are stopped to conserve power a transient state in which the cpu changes the processing flow due to a reset or an interrupt exception handling source. the cpu is initialized. note: see section 5, power-down modes, for details on the modes and their transitions. figure 2.14 cpu operation states 44 reset state program halt state exception-handling state program execution state reset cleared sleep instruction executed reset occurs interrupt source reset occurs exception- handling request exception- handling complete reset occurs figure 2.15 state transitions 2.7.2 program execution state in the program execution state the cpu executes program instructions in sequence. there are three modes in this state, two active modes (high speed and medium speed) and one subactive mode. operation is synchronized with the system clock in active mode (high speed and medium speed), and with the subclock in subactive mode. see section 5, power-down modes for details on these modes. 2.7.3 program halt state in the program halt state there are four modes: sleep mode, standby mode, watch mode, and subsleep mode. see section 5, power-down modes for details on these modes. 2.7.4 exception-handling state the exception-handling state is a transient state occurring when exception handling is started by a reset or interrupt and the cpu changes its normal processing flow. in exception handling caused by an interrupt, sp (r7) is referenced and the pc and ccr values are saved on the stack. for details on interrupt handling, see 3.3, interrupts. 45 2.8 memory map figure 2.16 shows a memory map for the h8/3627 series. interrupt vectors (42 bytes) on-chip rom on-chip ram reserved internal i/o registers (112 bytes) 16 kbytes h8/3622 h'0000 h'0029 h'002a h'9fff h'3fff h'5fff h'7fff h'ffff h'bfff h'edff h'eb80 h'f77f h'f780 h'ff7f h'ff80 h'ff8f h'ff90 reserved h8/3624 h8/3623 24 kbytes 32 kbytes 40 kbytes h8/3625 h8/3627 h8/3626 48 kbytes 60 kbytes 2 kbytes 1 kbyte figure 2.16 h8/3627 series memory map 46 2.9 application notes 2.9.1 notes on data access access to empty area: the address space of the h8/300l cpu includes empty areas in addition to the ram, registers, and rom areas available to the user. if these empty areas are mistakenly accessed by an application program, the following results will occur. data transfer from cpu to empty area: the transferred data will be lost. this action may also cause the cpu to misoperate. data transfer from empty area to cpu: unpredictable data is transferred. access to the internal i/o register: internal data transfer to or from on-chip modules other than the rom and ram areas makes use of an 8-bit data width. if word access is attempted to these areas, the following results will occur. word access from cpu to i/o register area: upper byte: will be written to i/o register. lower byte: transferred data will be lost. word access from i/o register to cpu: upper byte: will be written to upper part of cpu register. lower byte: unpredictable data will be written to lower part of cpu register. byte size instructions should therefore be used when transferring data to or from i/o registers other than the on-chip rom and ram areas. figure 2.17 shows the data size and number of states in which on-chip peripheral modules can be accessed. 47 word byte access states 2 or 3 2 : access possible : not possible interrupt vectors (42 bytes) on-chip rom on-chip ram reserved internal i/o registers (112 bytes) 16 kbytes h'0000 h'0029 h'002a h'9fff h'ffff h'3fff h'5fff h'7fff h'bfff h'fb80 h'edff h'f77f h'f780 h'ff7f h'ff80 h'ff8f h'ff90 reserved 24 kbytes 32 kbytes 2 kbytes 1 kbyte 2 h8/3622s h8/3624s h8/3623s 40 kbytes 48 kbytes 60 kbytes h8/3625 h8/3627 h8/3626 figure 2.17 data size and number of states for access to and from on-chip peripheral modules 48 2.9.2 notes on bit manipulation the bset, bclr, bnot, bst, and bist instructions read one byte of data, modify the data, then write the data byte again. special care is required when using these instructions in cases where two registers are assigned to the same address, in the case of registers that include write- only bits, and when the instruction accesses an i/o. order of operation operation 1 read read byte data at the designated address 2 modify modify a designated bit in the read data 3 write write the altered byte data to the designated address bit manipulation in two registers assigned to the same address example 1: bit manipulation to the timer load register and the timer counter figure 2.18 shows an example in which two timer registers share the same address. when a bit manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations take place. order of operation operation 1 read timer counter data is read (one byte) 2 modify the cpu modifies (sets or resets) the bit designated in the instruction 3 write the altered byte data is written to the timer load register the timer counter is counting, so the value read is not necessarily the same as the value in the timer load register. as a result, bits other than the intended bit in the timer load register may be modified to the timer counter value. r w r: w: read write count clock timer counter timer load register reload internal bus figure 2.18 timer configuration example 49 example 2: here a bset instruction is executed designating port 6. p6 7 and p6 6 are designated as input pins, with a low-level signal input at p6 7 and a high-level signal at p6 6 . the remaining pins, p6 5 to p6 0 , are output pins and output low-level signals. in this example, the bset instruction is used to change pin p6 0 to high-level output. [a: prior to executing bset] p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr6 00111111 pdr6 10000000 [b: bset instruction executed] bset #0, @pdr6 the bset instruction is executed designating port 6. [c: after executing bset] p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level high level pcr6 00111111 pdr6 0 100000 1 [d: explanation of how bset operates] when the bset instruction is executed, first the cpu reads port 6. since p6 7 and p6 6 are input pins, the cpu reads the pin states (low-level and high-level input). p6 5 to p6 0 are output pins, so the cpu reads the value in pdr6. in this example pdr6 has a value of h'80, but the value read by the cpu is h'40. next, the cpu sets bit 0 of the read data to 1, changing the pdr6 data to h'41. finally, the cpu writes this value (h'41) to pdr6, completing execution of bset. as a result of this operation, bit 0 in pdr6 becomes 1, and p6 0 outputs a high-level signal. however, bits 7 and 6 of pdr6 end up with different values. 50 to avoid this problem, store a copy of the pdr6 data in a work area in memory. perform the bit manipulation on the data in the work area, then write this data to pdr6. [a: prior to executing bset] mov. b #80, r0l mov. b r0l, @ram0 mov. b r0l, @pdr6 the pdr6 value (h'80) is written to a work area in memory (ram0) as well as to pdr6. p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr6 00111111 pdr6 10000000 ram0 10000000 [b: bset instruction executed] bset #0, @ram0 the bset instruction is executed designating the pdr6 work area (ram0). [c: after executing bset] mov. b @ram0, r0l mov. b r0l, @pdr6 the work area (ram0) value is written to pdr6. p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level high level pcr6 00111111 pdr6 1000000 1 ram0 1000000 1 51 bit manipulation in a register containing a write-only bit example 3: in this example, the port 6 control register pcr6 is accessed by a bclr instruction. as in the examples above, p6 7 and p6 6 are input pins, with a low-level signal input at p6 7 and a high-level signal at p6 6 . the remaining pins, p6 5 to p6 0 , are output pins that output low-level signals. in this example, the bclr instruction is used to change pin p6 0 to an input port. it is assumed that a high-level signal will be input to this input pin. [a: prior to executing bclr] p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr6 00111111 pdr6 10000000 [b: bclr instruction executed] bclr #0, @pcr6 the bclr instruction is executed designating pcr6. [c: after executing bclr] p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 input/output output output output output output output output input pin state low level high level low level low level low level low level low level high level pcr6 1 1 11111 0 pdr6 10000000 [d: explanation of how bclr operates] when the bclr instruction is executed, first the cpu reads pcr6. since pcr6 is a write-only register, the cpu reads a value of h'ff, even though the pcr6 value is actually h'3f. next, the cpu clears bit 0 in the read data to 0, changing the data to h'fe. finally, this value (h'fe) is written to pcr6 and bclr instruction execution ends. as a result of this operation, bit 0 in pcr6 becomes 0, making p6 0 an input port. however, bits 7 and 6 in pcr6 change to 1, so that p6 7 and p6 6 change from input pins to output pins. 52 to avoid this problem, store a copy of the pcr6 data in a work area in memory. perform the bit manipulation on the data in the work area, then write this data to pcr6. [a: prior to executing bclr] mov. b #3f , r0l mov. b r0l, @ram0 mov. b r0l, @pcr6 the pcr6 value (h'3f) is written to a work area in memory (ram0) as well as to pcr6. p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr6 00111111 pdr6 10000000 ram0 00111111 [b: bclr instruction executed] bclr #0, @ram0 the bclr instruction is executed designating the pcr6 work area (ram0). [c: after executing bclr] mov. b @ram0, r0l mov. b r0l, @pcr6 the work area (ram0) value is written to pcr6. p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level high level pcr6 0011111 0 pdr6 10000000 ram0 0011111 0 53 table 2.12 lists the registers with shared addresses. table 2.13 lists the registers that contain write- only bits. table 2.12 registers with shared addresses register name abbreviation address port data register 1 * pdr1 h'ffd4 port data register 2 * pdr2 h'ffd5 port data register 5 * pdr5 h'ffd8 port data register 6 * pdr6 h'ffd9 port data register 7 * pdr7 h'ffda port data register 8 * pdr8 h'ffdb port data register a * pdra h'ffdd note: * the port data register addresses are also assigned directly to input pins. table 2.13 registers with write-only bits register name abbreviation address port control register 1 pcr1 h'ffe4 port control register 2 pcr2 h'ffe5 port control register 5 pcr5 h'ffe8 port control register 6 pcr6 h'ffe9 port control register 7 pcr7 h'ffea port control register 8 pcr8 h'ffeb port control register a pcra h'ffed timer control register f tcrf h'ffb6 54 2.9.3 notes on use of the eepmov instruction the eepmov instruction is a block data transfer instruction. it moves the number of bytes specified by r4l from the address specified by r5 to the address specified by r6. ? r6 ? r6 + r4l r5 ? r5 + r4l ? when setting r4l and r6, make sure that the final destination address (r6 + r4l) does not exceed h'ffff. the value in r6 must not change from h'ffff to h'0000 during execution of the instruction. h'ffff not allowed ? r6 ? r6 + r4l r5 ? r5 + r4l ? 55 section 3 exception handling 3.1 overview exception handling is performed in the h8/3627 series when a reset or interrupt occurs. table 3.1 shows the priorities of these two types of exception handling. table 3.1 exception handling types and priorities priority exception source time of start of exception handling high reset exception handling starts as soon as the reset state is cleared low interrupt when an interrupt is requested, exception handling starts after execution of the present instruction or the exception handling in progress is completed 3.2 reset 3.2.1 overview a reset is the highest-priority exception. the internal state of the cpu and the registers of the on- chip peripheral modules are initialized. 3.2.2 reset sequence as soon as the res pin goes low, all processing is stopped and the h8/3637 series enters the reset state. to make sure the chip is reset properly, observe the following precautions. at power on: hold the res pin low until the clock pulse generator output stabilizes. when an external clock or ceramic oscillator is used, also, at power on the res pin must be held low for the crystal oscillator oscillation stabilization time shown in table 14.3 in section 14, electrical characteristics. resetting during operation: hold the res pin low for at least 18 system clock cycles. reset exception handling begins when the res pin is held low for a given period, then returned to the high level. reset exception handling takes place as follows. the cpu internal state and the registers of on-chip peripheral modules are initialized, with the i bit of the condition code register (ccr) set to 1. 56 the pc is loaded from the reset exception handling vector address (h'0000 to h'0001), after which the program starts executing from the address indicated in pc. when system power is turned on or off, the res pin should be held low. figure 3.1 shows the reset sequence. vector fetch ? internal address bus internal read signal internal write signal internal data bus (16-bit) res internal processing program initial instruction prefetch (1) reset exception handling vector address (h'0000) (2) program start address (3) first instruction of program (2) (3) (2) reset cleared (1) figure 3.1 reset sequence 3.2.3 interrupt immediately after reset after a reset, if an interrupt were to be accepted before the stack pointer (sp: r7) was initialized, pc and ccr would not be pushed onto the stack correctly, resulting in program runaway. to prevent this, immediately after reset exception handling all interrupts are masked. for this reason, the initial program instruction is always executed immediately after a reset. this instruction should initialize the stack pointer (e.g. mov.w #xx: 16, sp). 57 3.3 interrupts 3.3.1 overview the interrupt sources include 13 external interrupts (wkp 0 to wkp 7 , irq 0 to irq 4 ), and 16 internal interrupts from on-chip peripheral modules. table 3.2 shows the interrupt sources, their priorities, and their vector addresses. when more than one interrupt is requested, the interrupt with the highest priority is processed. the interrupts have the following features: internal and external interrupts can be masked by the i bit of ccr. when this bit is set to 1, interrupt request flags are set but interrupts are not accepted. irq 0 to irq 4 can each be set independently to either rising edge sensing or falling edge sensing. 58 table 3.2 interrupt sources and priorities interrupt source interrupt vector number vector address priority res reset 0 h'0000 to h'0001 high irq 0 irq 0 4 h'0008 to h'0009 irq 1 irq 1 5 h'000a to h'000b irq 2 irq 2 6 h'000c to h'000d irq 3 irq 3 7 h'000e to h'000f irq 4 irq 4 8 h'0010 to h'0011 wkp 0 wkp 0 9 h'0012 to h'0013 wkp 1 wkp 1 wkp 2 wkp 2 wkp 3 wkp 3 wkp 4 wkp 4 wkp 5 wkp 5 wkp 6 wkp 6 wkp 7 wkp 7 sci1 sci1 transfer complete 10 h'0014 to h'0015 timer a timer a overflow 11 h'0016 to h'0017 timer fl timer fl compare match timer fl overflow 14 h'001c to h'001d timer fh timer fh compare match timer fh overflow 15 h'001e to h'001f timer g timer g input capture timer g overflow 16 h'0020 to h'0021 sci3 sci3 receive data full sci3 transmit data empty sci3 transmit end sci3 overrun error sci3 framing error sci3 parity error 18 h'0024 to h'0025 a/d converter a/d conversion end 19 h'0026 to h'0027 (sleep instruction executed) direct transfer 20 h'0028 to h'0029 low note: vector addresses h'0002 to h'0007, h'0018 to h'001b, and h'0022 to h'0023 are reserved and cannot be used. 59 3.3.2 interrupt control registers table 3.3 lists the registers that control interrupts. table 3.3 interrupt control registers name abbreviation r/w initial value address interrupt edge select register iegr r/w h'60 h'fff2 interrupt enable register 1 ienr1 r/w h'00 h'fff3 interrupt enable register 2 ienr2 r/w h'01 h'fff4 interrupt request register 1 irr1 r/w * h'20 h'fff6 interrupt request register 2 irr2 r/w * h'01 h'fff7 wakeup interrupt request register iwpr r/w * h'00 h'fff9 note: * write is enabled only for writing of 0 to clear a flag. interrupt edge select register (iegr) bit 76543210 ieg4 ieg3 ieg2 ieg1 ieg0 initial value 01100000 read/write r/w r/w r/w r/w r/w iegr is an 8-bit read/write register, used to designate whether pins irq 0 to irq 4 are set to rising edge sensing or falling edge sensing. bit 7?reserved bit: bit 7 is reserved: it is always read as 0, and should be used cleared to 0. bits 6 and 5?reserved bits: bits 6 and 5 are reserved; they are always read as 1, and cannot be modified. bit 4?irq 4 edge select (ieg4): bit 4 selects the input sensing of pin irq 4 / adtrg . bit 4: ieg4 description 0 falling edge of irq 4 / adtrg pin input is detected (initial value) 1 rising edge of irq 4 / adtrg pin input is detected 60 bit 3?rq 3 edge select(ieg3): bit 3 selects the input sensing of pin irq 3 /tmif. bit 3: ieg3 description 0 falling edge of irq 3 /tmif pin input is detected (initial value) 1 rising edge of irq 3 /tmif pin input is detected bit 2?rq 2 edge select(ieg2): bit 2 selects the input sensing of pin irq 2 . bit 2: ieg2 description 0 falling edge of irq 2 pin input is detected (initial value) 1 rising edge of irq 2 pin input is detected bit 1?rq 1 edge select(ieg1): bit 1 selects the input sensing of pin irq 1 . bit 1: ieg1 description 0 falling edge of irq 1 pin input is detected (initial value) 1 rising edge of irq 1 pin input is detected bit 0?rq 0 edge select(ieg0): bit 0 selects the input sensing of pin irq 0 . bit 0: ieg0 description 0 falling edge of irq 0 pin input is detected (initial value) 1 rising edge of irq 0 pin input is detected 61 interrupt enable register 1 (ienr1) ienr1 is an 8-bit read/write register that enables or disables interrupt requests. bit 76543210 ienta iens1 ienwp ien4 ien3 ien2 ien1 ien0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w bit 7?imer a interrupt enable (ienta): bit 7 enables or disables timer a overflow interrupt requests. bit 7: ienta description 0 disables timer a interrupts (initial value) 1 enables timer a interrupts bit 6?ci1 interrupt enable (iens1): bit 6 enables or disables sci1 transfer complete interrupt requests. bit 6: iens1 description 0 disables sci1 interrupts (initial value) 1 enables sci1 interrupts bit 5?akeup interrupt enable (ienwp): bit 5 enables or disables wkp 7 to wkp 0 interrupt requests. bit 5: ienwp description 0 disables interrupt requests from wkp 7 to wkp 0 (initial value) 1 enables interrupt requests from wkp 7 to wkp 0 bits 4 to 0: irq 4 to irq 0 interrupt enable (ien4 to ien0): bits 4 to 0 enable or disable irq 4 to irq 0 interrupt requests. bits 4 to 0: ien4 to ien0 description 0 disables interrupt requests from irq 4 to irq 0 (initial value) 1 enables interrupt requests from irq 4 to irq 0 62 interrupt enable register 2 (ienr2) bit 76543210 iendt ienad ientg ientfh ientfl initial value 00000001 read/write r/w r/w r/w r/w r/w ienr2 is an 8-bit read/write register that enables or disables interrupt requests. bit 7?irect transfer interrupt enable (iendt): bit 7 enables or disables direct transfer interrupt requests. bit 7: iendt description 0 disables direct transfer interrupt requests (initial value) 1 enables direct transfer interrupt requests bit 6?/d converter interrupt enable (ienad): bit 6 enables or disables a/d converter end interrupt requests. bit 6: ienad description 0 disables a/d converter interrupt requests (initial value) 1 enables a/d converter interrupt requests bit 5?eserved bit: bit 5 is reserved: it is always read as 0, and should be used cleared to 0. bit 4?imer g interrupt enable (ientg): bit 4 enables or disables timer g input capture and overflow interrupt requests. bit 4: ientg description 0 disables timer g interrupts (initial value) 1 enables timer g interrupts bit 3?imer fh interrupt enable (ientfh): bit 3 enables or disables timer fh compare match and overflow interrupt requests. bit 3: ientfh description 0 disables timer fh interrupts (initial value) 1 enables timer fh interrupts 63 bit 2?imer fl interrupt enable (ientfl): bit 2 enables or disables timer fl compare match and overflow interrupt requests. bit 2: ientfl description 0 disables timer fl interrupts (initial value) 1 enables timer fl interrupts bit 1?eserved bit: bit 1 is reserved: it is always read as 0, and should be used cleared to 0. bit 0?eserved bit: bit 0 is reserved: it is always read as 1, and cannot be modified. for details of sci3 interrupt control, see serial control register 3 (scr3), in section 10.3.2. interrupt request register 1 (irr1) bit 76543210 irrta irrs1 irri4 irri3 irri2 irri1 irri0 initial value 00100000 read/write r/w * r/w * r/w * r/w * r/w * r/w * r/w * note: * only a write of 0 for flag clearing is possible. irr1 is an 8-bit read/write register, in which the corresponding bit is set to 1 when a timer a, sci1, or irq 4 to irq 0 interrupt is requested. the flags are not cleared automatically when an interrupt is accepted. it is necessary to write 0 to clear each flag. bit 7?imer a interrupt request flag (irrta) bit 7: irrta description 0 [clearing conditions] (initial value) when irrta = 1, it is cleared by writing 0 1 [setting conditions] when the timer a counter value overflows (goes from h'ff to h'00) bit 6?ci1 interrupt request flag (irrs1) bit 6: irrs1 description 0 [clearing conditions] (initial value) when irrs1 = 1, it is cleared by writing 0 1 [setting conditions] when an sci1 transfer is completed 64 bit 5?eserved bit: bit 5 is reserved; it is always read as 1, and cannot be modified. bits 4 to 0?rq 4 to irq 0 interrupt request flags (irri4 to irri0) bits 4 to 0: irri4 to irri0 description 0 [clearing conditions] (initial value) when irrin = 1, it is cleared by writing 0 to irrin. 1 [setting conditions] irrin is set when pin irq n is set to interrupt input, and the designated signal edge is detected. (n = 4 to 0) interrupt request register 2 (irr2) bit 76543210 irrdt irrad irrtg irrtfh irrtfl initial value 00000001 read/write r/w * r/w * r/w * r/w * r/w * note: * only a write of 0 for flag clearing is possible. irr2 is an 8-bit register containing direct transfer, a/d converter, timer g, timer fh, and timer fl, interrupt flags. when a direct transfer, a/d converter, timer g, timer fh, or timer fl, interrupt is requested, the corresponding flag is set to 1. the flags are not cleared automatically when an interrupt is accepted. it is necessary to write 0 to clear each flag. bit 7?irect transfer interrupt request flag (irrdt) bit 7: irrdt description 0 [clearing conditions] (initial value) when irrdt = 1, it is cleared by writing 0 1 [setting conditions] when dton = 1 and a direct transfer is made immediately after a sleep instruction is executed 65 bit 6?/d converter interrupt request flag (irrad) bit 6: irrad description 0 [clearing conditions] (initial value) when irrad = 1, it is cleared by writing 0 1 [setting conditions] when a/d conversion is completed and adsf is reset bit 5?eserved bit: bit 5 is reserved: it is always read as 0, and should be used cleared to 0. bit 4?imer g interrupt request flag (irrtg) bit 4: irrtg description 0 [clearing conditions] (initial value) when irrtg = 1, it is cleared by writing 0 1 [setting conditions] when pin tmig is set to tmig input and the designated signal edge is detected, or when tcg overflows (from h?f to h?0) while tmg ovie is set to 1 bit 3?imer fh interrupt request flag (irrtfh) bit 3: irrtfh description 0 [clearing conditions] (initial value) when irrtfh = 1, it is cleared by writing 0 1 [setting conditions] when counter fh matches output compare register fh in 8-bit timer mode, or when 16-bit counter f (tcfl, tcfh) matches output compare register f (ocrfl, ocrfh) in 16-bit timer mode bit 2?imer fl interrupt request flag (irrtfl) bit 2: irrtfl description 0 [clearing conditions] (initial value) when irrtfl = 1, it is cleared by writing 0 1 [setting conditions] when counter fl matches output compare register fl in 8-bit timer mode bit 1?eserved bit: bit 1 is reserved: it is a always read as 0, and should be used cleared to 0. bit 0?eserved bit: bit 0 is reserved: it is a always read as 1, and cannot be modified. 66 wakeup interrupt request register (iwpr) bit 76543210 iwpf7 iwpf6 iwpf5 iwpf4 iwpf3 iwpf2 iwpf1 iwpf0 initial value 00000000 read/write r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * note: * only a write of 0 for flag clearing is possible. iwpr is an 8-bit read/write register, in which the corresponding bit is set to 1 when pins wkp 7 to wkp 0 are set to wakeup input and a pin receives a falling edge input. the flags are not cleared automatically when an interrupt is accepted. it is necessary to write 0 to clear each flag. bits 7 to 0?wakeup interrupt request flags (iwpf7 to iwpf0) bits 7 to 0: iwpf7 to iwpf0 description 0 [clearing conditions] (initial value) when iwpfn = 1, it is cleared by writing 0 to iwpfn. 1 [setting conditions] iwpfn is set when pin wkp n is set to wakeup interrupt input, and a falling edge input is detected at the pin. (n = 7 to 0) 67 3.3.3 external interrupts there are 13 external interrupts, wkp 0 to wkp 7 and irq 0 to irq 4 . interrupts wkp 0 to wkp 7 : interrupts wkp 0 to wkp 7 are requested by falling edge inputs at pins wkp 0 to wkp 7 . when these pins are designated as wkp 0 to wkp 7 pins in port mode register 5 (pmr5) and falling edge input is detected, the corresponding bit in the wakeup interrupt request register (iwpr) is set to 1, requesting an interrupt. wakeup interrupt requests can be disabled by clearing the ienwp bit in ienr1 to 0. it is also possible to mask all interrupts by setting the ccr i bit to 1. when an interrupt exception handling request is received for interrupts wkp 0 to wkp 7 , the ccr i bit is set to 1. the vector number for interrupts wkp 0 to wkp 7 is 9. since all eight interrupts are assigned the same vector number, the interrupt source must be determined by the exception handling routine. interrupts irq 0 to irq 4 : interrupts irq 0 to irq 4 are requested by inputs into pins irq 0 to irq 4 . these interrupts are detected by either rising edge sensing or falling edge sensing, depending on the settings of bits ieg0 to ieg4 in the edge select register (iegr). when these pins are designated as pins irq 0 to irq 4 in port mode registers 1 and 2 (pmr1 and pmr2) and the designated edge is input, the corresponding bit in irr1 is set to 1, requesting an interrupt. interrupts irq 0 to irq 4 can be disabled by clearing bits ien0 to ien4 in ienr1 to 0. all interrupts can be masked by setting the i bit in ccr to 1. when irq 0 to irq 4 interrupt exception handling is initiated, the i bit in ccr is set to 1. vector numbers 4 to 8 are assigned to interrupts irq 0 to irq 4 . the order of priority is from irq 0 (high) to irq 4 (low). table 3.2 gives details. 3.3.4 internal interrupts there are 16 internal interrupts that can be requested by the on-chip peripheral modules. when a peripheral module requests an interrupt, the corresponding bit in irr1 or irr2 is set to 1. individual interrupt requests can be disabled by clearing the corresponding bit in ienr1 or ienr2 to 0. all interrupts can be masked by setting the i bit in ccr to 1. when an internal interrupt request is accepted, the i bit in ccr is set to 1. vector numbers 10 to 20 are assigned to these interrupts. table 3.2 shows the order of priority of interrupts from on-chip peripheral modules. 68 3.3.5 interrupt operations interrupts are controlled by an interrupt controller. figure 3.2 shows a block diagram of the interrupt controller. figure 3.3 shows the flow up to interrupt acceptance. interrupt controller priority decision logic interrupt request ccr (cpu) i external or internal interrupts external interrupts or internal interrupt enable signals figure 3.2 block diagram of interrupt controller 69 interrupt operation is described as follows. 1. when an interrupt condition is met while the interrupt enable register bit is set to 1, an interrupt request signal is sent to the interrupt controller. 2. when the interrupt controller receives an interrupt request, it sets the interrupt request flag. 3. from among the interrupts with interrupt request flags set to 1, the interrupt controller selects the interrupt request with the highest priority and holds the others pending. (refer to table 3.2 for a list of interrupt priorities.) 4. the interrupt controller checks the i bit of ccr. if the i bit is 0, the selected interrupt request is accepted; if the i bit is 1, the interrupt request is held pending. 5. if the interrupt is accepted, after processing of the current instruction is completed, both pc and ccr are pushed onto the stack. the state of the stack at this time is shown in figure 3.4. the pc value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling. 6. the i bit of ccr is set to 1, masking all further interrupts. 7. the vector address corresponding to the accepted interrupt is generated, and the interrupt handling routine located at the address indicated by the contents of the vector address is executed. notes: 1. when disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in an interrupt request register, always do so while interrupts are masked (i = 1). 2. if the above clear operations are performed while i = 0, and as a result a conflict arises between the clear instruction and an interrupt request, exception processing for the interrupt will be executed after the clear instruction has been executed. 70 pc contents saved ccr contents saved i ? 1 i = 0 program execution state no yes yes no legend: pc: ccr: i: program counter condition code register i bit of ccr ien0 = 1 no yes iendt = 1 no yes irrdt = 1 no yes branch to interrupt handling routine irri0 = 1 no yes ien1 = 1 no yes irri1 = 1 no yes ien2 = 1 no yes irri2 = 1 figure 3.3 flow up to interrupt acceptance 71 pc and ccr saved to stack sp (r7) sp ?1 sp ?2 sp ?3 sp ?4 stack area sp + 4 sp + 3 sp + 2 sp + 1 sp (r7) even address prior to start of interrupt exception handling after completion of interrupt exception handling legend: pc h : pc l : ccr: sp: upper 8 bits of program counter (pc) lower 8 bits of program counter (pc) condition code register stack pointer * ignored on return from interrupt. notes: ccr ccr * pc h pc l 1. 2. pc shows the address of the first instruction to be executed upon return from the interrupt handling routine. register contents must always be saved and restored by word access, starting from an even-numbered address. figure 3.4 stack state after completion of interrupt exception handling figure 3.5 shows a typical interrupt sequence where the program area is in the on-chip rom and the stack area is in the on-chip ram. 72 vector fetch internal address bus internal read signal internal write signal (2) internal data bus (16 bits) interrupt request signal (9) (1) internal processing prefetch instruction of interrupt-handling routine (1) instruction prefetch address (instruction is not executed. address is saved as pc contents, becoming return address.) (2)(4) instruction code (not executed) (3) instruction prefetch address (instruction is not executed.) (5) sp ?2 (6) sp ?4 (7) ccr (8) vector address (9) starting address of interrupt-handling routine (contents of vector) (10) first instruction of interrupt-handling routine (3) (9) (8) (6) (5) (4) (1) (7) (10) stack access internal processing instruction prefetch interrupt level decision and wait for end of instruction interrupt is accepted figure 3.5 interrupt sequence 73 3.3.6 interrupt response time table 3.4 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handler is executed. table 3.4 interrupt wait states item states total waiting time for completion of executing instruction * 1 to 13 15 to 27 saving of pc and ccr to stack 4 vector fetch 2 instruction fetch 4 internal processing 4 note: * not including eepmov instruction. 74 3.4 application notes 3.4.1 notes on stack area use when word data is accessed in the h8/3637 series, the least significant bit of the address is regarded as 0. access to the stack always takes place in word size, so the stack pointer (sp: r7) should never indicate an odd address. use push rn (mov.w rn, @?p) or pop rn (mov.w @sp+, rn) to save or restore register values. setting an odd address in sp may cause a program to crash. an example is shown in figure 3.6. pc pc r1l pc sp sp sp h'fefc h'fefd h'feff ? ? ? h l l mov. b r1l, @er7 sp set to h'feff stack accessed beyond sp bsr instruction contents of pc are lost h legend: pc h : pc l : r1l: sp: upper byte of program counter lower byte of program counter general register r1l stack pointer figure 3.6 operation when odd address is set in sp when ccr contents are saved to the stack during interrupt exception handling or restored when rte is executed, this also takes place in word size. both the upper and lower bytes of word data are saved to the stack; on return, the even address contents are restored to ccr while the odd address contents are ignored. 3.4.2 notes on rewriting port mode registers when a port mode register is rewritten to switch the functions of external interrupt pins, the following points should be observed. 75 when an external interrupt pin function is switched by rewriting the port mode register that controls these pins ( irq 4 to irq 0 , and wkp 7 to wkp 0 ), the interrupt request flag may be set to 1 at the time the pin function is switched, even if no valid interrupt is input at the pin. be sure to clear the interrupt request flag to 0 after switching pin functions. table 3.5 shows the conditions under which interrupt request flags are set to 1 in this way. table 3.5 conditions under which interrupt request flag is set to 1 interrupt request flags set to 1 conditions irr1 irri4 when pmr2 bit irq4 is changed from 0 to 1 while pin irq 4 is low and iegr bit ieg4 = 0. when pmr2 bit irq4 is changed from 1 to 0 while pin irq 4 is low and iegr bit ieg4 = 1. irri3 when pmr1 bit irq3 is changed from 0 to 1 while pin irq 3 is low and iegr bit ieg3 = 0. when pmr1 bit irq3 is changed from 1 to 0 while pin irq 3 is low and iegr bit ieg3 = 1. irri2 when pmr1 bit irq2 is changed from 0 to 1 while pin irq 2 is low and iegr bit ieg2 = 0. when pmr1 bit irq2 is changed from 1 to 0 while pin irq 2 is low and iegr bit ieg2 = 1. irri1 when pmr1 bit irq1 is changed from 0 to 1 while pin irq 1 is low and iegr bit ieg1 = 0. when pmr1 bit irq1 is changed from 1 to 0 while pin irq 1 is low and iegr bit ieg1 = 1. irri0 when pmr2 bit irq0 is changed from 0 to 1 while pin irq 0 is low and iegr bit ieg0 = 0. when pmr2 bit irq0 is changed from 1 to 0 while pin irq 0 is low and iegr bit ieg0 = 1. iwpr iwpf7 when pmr5 bit wkp7 is changed from 0 to 1 while pin wkp 7 is low iwpf6 when pmr5 bit wkp6 is changed from 0 to 1 while pin wkp 6 is low iwpf5 when pmr5 bit wkp5 is changed from 0 to 1 while pin wkp 5 is low iwpf4 when pmr5 bit wkp4 is changed from 0 to 1 while pin wkp 4 is low iwpf3 when pmr5 bit wkp3 is changed from 0 to 1 while pin wkp 3 is low iwpf2 when pmr5 bit wkp2 is changed from 0 to 1 while pin wkp 2 is low iwpf1 when pmr5 bit wkp1 is changed from 0 to 1 while pin wkp 1 is low iwpf0 when pmr5 bit wkp0 is changed from 0 to 1 while pin wkp 0 is low 76 figure 3.7 shows the procedure for setting a bit in a port mode register and clearing the interrupt request flag. when switching a pin function, mask the interrupt before setting the bit in the port mode register. after accessing the port mode register, execute at least one instruction (e.g., nop), then clear the interrupt request flag from 1 to 0. if the instruction to clear the flag is executed immediately after the port mode register access without executing an intervening instruction, the flag will not be cleared. an alternative method is to avoid the setting of interrupt request flags when pin functions are switched by keeping the pins at the high level so that the conditions in table 3.5 do not occur. ccr i bit 1 set port mode register bit execute nop instruction interrupts masked. (another possibility is to disable the relevant interrupt in interrupt enable register 1.) after setting the port mode register bit, first execute at least one instruction (e.g., nop), then clear the interrupt request flag to 0 interrupt mask cleared clear interrupt request flag to 0 ? ccr i bit 0 ? figure 3.7 port mode register setting and interrupt request flag clearing procedure 77 section 4 clock pulse generators 4.1 overview clock oscillator circuitry (cpg: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. the system clock pulse generator consists of a system clock oscillator and system clock dividers. the subclock pulse generator consists of a subclock oscillator circuit and a subclock divider. 4.1.1 block diagram figure 4.1 shows a block diagram of the clock pulse generators. system clock oscillator system clock divider (1/2) subclock oscillator subclock divider (1/2, 1/4, 1/8) system clock divider (1/8) system clock pulse generator subclock pulse generator prescaler s (13 bits) prescaler w (5 bits) osc osc 1 2 x x 1 2 osc (f ) osc w (f ) w ? /2 osc ? /2 w ? /8 w sub ?2 to ?8192 ? /2 w ? /4 w ? /8 to ? /128 w w ? /16 osc ? /4 w w osc figure 4.1 block diagram of clock pulse generators 4.1.2 system clock and subclock the basic clock signals that drive the cpu and on-chip peripheral modules are ?and sub . four of the clock signals have names: ?is the system clock, sub is the subclock, osc is the oscillator clock, and w is the watch clock. the clock signals available for use by peripheral modules are osc , ?2, ?4, ?8, ?16, ?32, ?64, ?128, ?256, ?512, ?1024, ?2048, ?4096, ?8192, w , w /2, w /4, w /8, w /16, w /32, w /64, and w /128. the clock requirements differ from one module to another. 78 4.2 system clock generator clock pulse can be supplied to the system clock divider either by connecting a crystal or ceramic oscillator, or by providing external clock input. connecting a crystal oscillator: figure 4.2 shows a typical method of connecting a crystal oscillator. 1 2 c 1 c 2 osc osc r = 1 m 20% c = c = 12 pf 20% f 12 w r f figure 4.2 typical connection to crystal oscillator figure 4.3 shows the equivalent circuit of a crystal oscillator. an oscillator having the characteristics given in table 4.1 should be used. c s c 0 r s osc 1 osc 2 l s figure 4.3 equivalent circuit of crystal oscillator table 4.1 crystal oscillator parameters frequency 2 mhz 4 mhz 8 mhz 10 mhz r s (max) 500 w 100 w 50 w 30 w c 0 (max) 7 pf 7 pf 7 pf 7 pf 79 connecting a ceramic oscillator: figure 4.4 shows a typical method of connecting a ceramic oscillator. 1 2 c 1 c 2 osc osc r f = 1 m w 20% c 1 = 30 pf 10% c 2 = 30 pf 10% ceramic oscillator: murata r f figure 4.4 typical connection to ceramic oscillator notes on board design: when generating clock pulses by connecting a crystal or ceramic oscillator, pay careful attention to the following points. avoid running signal lines close to the oscillator circuit, since the oscillator may be adversely affected by induction currents. (see figure 4.5.) the board should be designed so that the oscillator and load capacitors are located as close as possible to pins osc 1 and osc 2 . osc osc c 1 c 2 signal a signal b 2 1 to be avoided figure 4.5 board design of oscillator circuit 80 external clock input method: connect an external clock signal to pin osc 1 , and leave pin osc 2 open. figure 4.6 shows a typical connection. 1 2 osc osc external clock input open figure 4.6 external clock input (example) frequency oscillator clock ( osc ) duty cycle 45% to 55% 81 4.3 subclock generator connecting a 32.768-khz crystal oscillator: clock pulses can be supplied to the subclock divider by connecting a 32.768-khz crystal oscillator, as shown in figure 4.7. follow the same precautions as noted in 4.2, notes on board design. x x c 1 c 2 1 2 c = c = 15 pf (typ.) 12 figure 4.7 typical connection to 32.768-khz crystal oscillator figure 4.8 shows the equivalent circuit of the 32.768-khz crystal oscillator. c s c 0 lr s x 1 x 2 c = 1.5 pf typ r = 14 k typ f = 32.768 khz crystal oscillator: mx38t (nihon denpa kogyo) 0 s w w s figure 4.8 equivalent circuit of 32.768-khz crystal oscillator pin connection when not using subclock: when the subclock is not used, connect pin x 1 to v cc and leave pin x 2 open, as shown in figure 4.9. x x 1 2 v cc open figure 4.9 pin connection when not using subclock 82 4.4 prescalers the h8/3637 series is equipped with two on-chip prescalers having different input clocks (prescaler s and prescaler w). prescaler s is a 13-bit counter using the system clock (? as its input clock. its prescaled outputs provide internal clock signals for on-chip peripheral modules. prescaler w is a 5-bit counter using a 32.768-khz signal divided by 4 ( w /4) as its input clock. its prescaled outputs are used by timer a as a time base for timekeeping. prescaler s (pss): prescaler s is a 13-bit counter using the system clock (? as its input clock. it is incremented once per clock period. prescaler s is initialized to h'0000 by a reset, and starts counting on exit from the reset state. in standby mode, watch mode, subactive mode, and subsleep mode, the system clock pulse generator stops. prescaler s also stops and is initialized to h'0000. the cpu cannot read or write prescaler s. the output from prescaler s is shared by the on-chip peripheral modules. the divider ratio can be set separately for each on-chip peripheral function. in active (medium-speed) mode the clock input to prescaler s is osc /16. prescaler w (psw): prescaler w is a 5-bit counter using a 32.768 khz signal divided by 4 ( w /4) as its input clock. prescaler w is initialized to h'00 by a reset, and starts counting on exit from the reset state. even in standby mode, watch mode, subactive mode, or subsleep mode, prescaler w continues functioning so long as clock signals are supplied to pins x 1 and x 2 . prescaler w can be reset by setting 1s in bits tma3 and tma2 of timer mode register a (tma). output from prescaler w can be used to drive timer a, in which case timer a functions as a time base for timekeeping. 4.5 note on oscillators oscillator characteristics of both the masked rom and ztat tm versions are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section and figure 4.10, example of crystal and ceramic oscillator layout. oscillator circuit constants will differ depending on the oscillator element, stray capacitance in its interconnecting circuit, and other factors. suitable constants should be determined in consultation with the oscillator element manufacturer. design the circuit so that the oscillator element never receives voltages exceeding its maximum rating. 83 x x 1 2 v ss cv cc osc 2 osc test (vss) 1 figure 4.10 example of crystal and ceramic oscillator layout. 84 85 section 5 power-down modes 5.1 overview the h8/3627 series has seven modes of operation after a reset. these include six power-down modes, in which power dissipation is significantly reduced. table 5.1 gives a summary of the seven operation modes. table 5.1 operation modes operating mode description active (high-speed) mode the cpu runs on the system clock, executing program instructions at high speed active (medium-speed) mode the cpu runs on the system clock, executing program instructions at reduced speed subactive mode the cpu runs on the subclock, executing program instructions at reduced speed sleep mode the cpu halts. on-chip peripheral modules continue to operate on the system clock. subsleep mode the cpu halts. timer a, and timer g, continue to operate on the subclock. watch mode the cpu halts. the time-base function of timer a continues to operate on the subclock. standby mode the cpu and all on-chip peripheral modules stop operating all but the active (high-speed) mode are power-down modes. in this section the two active modes (high-speed and medium-speed) are referred to collectively as active mode. figure 5.1 shows the transitions among these operation modes. table 5.2 indicates the internal states in each mode. 86 reset state program executing program execution stopped program execution stopped active (high-speed) mode power-down mode sleep instruction sleep instruction sleep instruction sleep instruction sleep instruction sleep instruction notes: timer a interrupt, irq interrupt, wkp to wkp interrupts timer a interrupt, timer g interrupt, irq 0 to irq 4 interrupts, wkp 0 to wkp 7 interrupts all interrupts 1. 2. 3. 4. 007 01 07 2 * 1 * 1 * 4 * 4 * 1 * 3 * 3 * lson = 1, tma3 = 1 lson = 0, mson = 1 lson = 0, mson = 0 ssby = 0, lson = 1, tma3 = 1 ssby = 0, lson = 0 ssby = 1, tma3 = 0, lson = 0 ssby = 1, tma3 = 1 sleep instruction dton = 1 dton = 1 dton = 1 sleep instruction a transition between different modes cannot be made to occur simply because an interrupt request is generated. make sure that the interrupt is accepted and interrupt handling is performed. : transition caused by exception handling ? subsleep mode subactive mode watch mode active (medium-speed) mode standby mode details on the mode transition conditions are given in the explanations of each mode, in sections 5.2 through 5.8. sleep mode irq interrupt, irq interrupt, wkp to wkp interrupts figure 5.1 operation mode transition diagram 87 table 5.2 internal state in each operation mode active mode function high speed medium speed sleep mode watch mode subactive mode subsleep mode standby mode system clock oscillator functional functional functional stopped stopped stopped stopped subclock oscillator functional functional functional functional functional functional functional cpu instructions functional functional stopped stopped functional stopped stopped operation ram retained retained retained retained registers i/o retained * 1 external irq 0 functional functional functional functional functional functional functional interrupts irq 1 retained * 4 irq 2 retained * 4 irq 3 irq 4 wkp 0 functional functional functional functional functional functional functional wkp 1 wkp 2 wkp 3 wkp 4 wkp 5 wkp 6 wkp 7 peripheral timer a functional functional functional functional * 3 functional * 3 functional * 3 retained module timer f retained retained retained functions timer g functional/ retained * 2 functional/ retained * 2 sci1 functional functional functional retained retained retained retained sci3 reset reset reset reset dtmf functional functional functional reset reset reset reset a/d functional functional functional retained retained retained retained notes: 1. register contents held; high-impedance output. 2. functional only if w /2 internal clock is selected; otherwise stopped and retained. 3. functional when timekeeping time-base function is selected. 4. external interrupt requests are ignored. the interrupt request register contents are not affected. 88 5.1.1 system control registers the operation mode is selected using the system control registers described in table 5.3. table 5.3 system control register name abbreviation r/w initial value address system control register 1 syscr1 r/w h'07 h'fff0 system control register 2 syscr2 r/w h'e0 h'fff1 system control register 1 (syscr1) bit 76543210 ssby sts2 sts1 sts0 lson initial value 00000111 read/write r/w r/w r/w r/w r/w syscr1 is an 8-bit read/write register for control of the power-down modes. upon reset, syscr1 is initialized to h'07. bit 7?oftware standby (ssby): this bit designates transition to standby mode or watch mode. bit 7: ssby description 0 when a sleep instruction is executed in active mode, a transition is made to sleep mode. when a sleep instruction is executed in subactive mode, a transition is made to subsleep mode. (initial value) 1 when a sleep instruction is executed in active mode, a transition is made to standby mode or watch mode. when a sleep instruction is executed in subactive mode, a transition is made to watch mode. bits 6 to 4?tandby timer select 2 to 0 (sts2 to sts0): these bits designate the time the cpu and peripheral modules wait for stable clock operation after exiting from standby mode or watch mode to active mode due to an interrupt. the designation should be made according to the clock frequency so that the waiting time is at least 10 ms. 89 bit 6: sts2 bit 5: sts1 bit 4: sts0 description 0 0 0 wait time = 8,192 states (initial value) 1 wait time = 16,384 states 1 0 wait time = 32,768 states 1 wait time = 65,536 states 1 ** wait time = 131,072 states note: * don? care bit 3?ow speed on flag (lson): this bit chooses the system clock (? or subclock ( sub ) as the cpu operating clock when watch mode is cleared. the resulting operation mode depends on the combination of other control bits and interrupt input. bit 3: lson description 0 the cpu operates on the system clock (? (initial value) 1 the cpu operates on the subclock ( sub ) bits 2 to 0?eserved bits: these bits are reserved; they are always read as 1, and cannot be modified. system control register 2 (syscr2) bit 76543210 nesel dton mson sa1 sa0 initial value 11100000 read/write r/w r/w r/w r/w r/w syscr2 is an 8-bit read/write register for power-down mode control. upon reset, syscr2 is initialized to h'e0. bits 7 to 5?eserved bits: these bits are reserved; they are always read as 1, and cannot be modified. 90 bit 4?noise elimination sampling frequency select (nesel): this bit selects the frequency at which the watch clock signal ( w ) generated by the subclock pulse generator is sampled, in relation to the oscillator clock ( osc ) generated by the system clock pulse generator. when osc = 2 to 10 mhz, clear nesel to 0. bit 4: nesel description 0 sampling rate is osc /16 (initial value) 1 sampling rate is osc /4 bit 3?irect transfer on flag (dton): this bit designates whether or not to make direct transitions among active (high-speed), active (medium-speed) and subactive mode when a sleep instruction is executed. the mode to which the transition is made after the sleep instruction is executed depends on a combination of this and other control bits. bit 3: dton description 0 when a sleep instruction is executed in active mode, a transition is made to standby mode, watch mode, or sleep mode. (initial value) when a sleep instruction is executed in subactive mode, a transition is made to watch mode or subsleep mode. 1 when a sleep instruction is executed in active (high-speed) mode, a direct transition is made to active (medium-speed) mode if ssby = 0, mson = 1, and lson = 0, or to subactive mode if ssby = 1, tma3 = 1, and lson = 1. when a sleep instruction is executed in active (medium-speed) mode, a direct transition is made to active (high-speed) mode if ssby = 0, mson = 0, and lson = 0, or to subactive mode if ssby = 1, tma3 = 1, and lson = 1. when a sleep instruction is executed in subactive mode, a direct transition is made to active (high-speed) mode if ssby = 1, tma3 = 1, lson = 0, and mson = 0, or to active (medium-speed) mode if ssby = 1, tma3 = 1, lson = 0, and mson = 1. bit 2?edium speed on flag (mson): after standby, watch, or sleep mode is cleared, this bit selects active (high-speed) or active (medium-speed) mode. bit 2: mson description 0 operation is in active (high-speed) mode (initial value) 1 operation is in active (medium-speed) mode 91 bits 1 and 0?ubactive mode clock select (sa1 and sa0): these bits select the cpu clock rate ( w /2, w /4, or w /8) in subactive mode. sa1 and sa0 cannot be modified in subactive mode. bit 1: sa1 bit 0: sa0 description 00 w /8 (initial value) 1 w /4 1 * w /2 note: * don? care 5.2 sleep mode 5.2.1 transition to sleep mode the system goes from active mode to sleep mode when a sleep instruction is executed while the ssby and lson bits in system control register 1 (syscr1) are cleared to 0. in sleep mode cpu operation is halted but the on-chip peripheral functions are operational. the cpu register contents are retained. 5.2.2 clearing sleep mode sleep mode is cleared by an interrupt (timer a, timer f, timer g, irq 0 to irq 4 , wkp 0 to wkp 7 , sci1, sci3, a/d converter) or by reset input. clearing by interrupt: when an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. operation resumes in active (high-speed) mode if mson = 0 in syscr2, or active (medium-speed) mode if mson = 1. sleep mode is not cleared if the i bit of the condition code register (ccr) is set to 1 or the particular interrupt is disabled in the interrupt enable register. clearing by reset input: when the res pin goes low, the cpu goes into the reset state and sleep mode is cleared. 92 5.3 standby mode 5.3.1 transition to standby mode the system goes from active mode to standby mode when a sleep instruction is executed while the ssby bit in syscr1 is set to 1, the lson bit is cleared to 0, and bit tma3 in timer mode register a (tma) is cleared to 0. in standby mode the clock pulse generator stops, so the cpu and on-chip peripheral modules stop functioning. as long as a minimum required voltage is applied, the contents of the cpu registers and some on-chip peripheral function internal registers, and data in the on-chip ram, will be retained. the i/o ports go to the high-impedance state. 5.3.2 clearing standby mode standby mode is cleared by an interrupt (irq 0 , irq 1 , wkp 0 to wkp 7 ) or by input at the res pin. clearing by interrupt: when an interrupt is requested, the system clock pulse generator starts. after the time set in bits sts2 to sts0 in syscr1 has elapsed, a stable system clock signal is supplied to the entire chip, standby mode is cleared, and interrupt exception handling starts. operation resumes in active (high-speed) mode if mson = 0 in syscr2, or active (medium- speed) mode if mson = 1. standby mode is not cleared if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. clearing by res input: when the res pin goes low, the system clock pulse generator starts. after the pulse generator output has stabilized, if the res pin is driven high, the cpu starts reset exception handling. since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the res pin should be kept at the low level until the pulse generator output stabilizes. 93 5.3.3 oscillator settling time after standby mode is cleared bits sts2 to sts0 in syscr1 should be set as follows. when a crystal oscillator is used: table 5.4 gives settings for various operating frequencies. set bits sts2 to sts0 for a waiting time of at least 10 ms. table 5.4 clock frequency and settling time (times are in ms) sts2 sts1 sts0 waiting time 5 mhz 4 mhz 2 mhz 1 mhz 0.5 mhz 0 0 0 8,192 states 1.6 2.0 4.1 8.2 16.4 0 0 1 16,384 states 3.2 4.1 8.2 16.4 32.8 0 1 0 32,768 states 6.6 8.2 16.4 32.8 65.5 0 1 1 65,536 states 13.1 16.4 32.8 65.5 131.1 1 ** 131,072 states 26.2 32.8 65.5 131.1 262.1 note: * don? care when an external clock is used: any values may be set. normally the minimum time (sts2 = sts1 = sts0 = 0) should be set. 94 5.3.4 transition to standby mode and pin states the system goes from active (high-speed) mode or active (medium-speed) mode to standby mode when a sleep instruction is executed while the ssby bit in syscr1 is set to 1, the lson bit in syscr1 is cleared to 0, and bit tma3 in tma is cleared to 0. at the same time, pins go to the high-impedance state (except pins with mos pull-up turned on). the timing in this case is shown in figure 5.2. sleep instruction fetch internal data bus next instruction fetch port output pins high impedance active (high-speed) mode or active (medium-speed) mode standby mode sleep instruction execution internal processing figure 5.2 transition to standby mode and pin states 95 5.4 watch mode 5.4.1 transition to watch mode the system goes from active or subactive mode to watch mode when a sleep instruction is executed while the ssby bit in syscr1 is set to 1 and bit tma3 in tma is set to 1. in watch mode, operation of on-chip peripheral modules other than timer a is halted. as long as a minimum required voltage is applied, the contents of cpu registers and some registers of the on- chip peripheral modules*, and the on-chip ram contents, are retained. i/o ports keep the same states as before the transition. note: * the contents of sci3, dtmf generator registers are reset. 5.4.2 clearing watch mode watch mode is cleared by an interrupt (timer a, irq 0 , wkp 0 to wkp 7 ) or by a low input at the res pin. clearing by interrupt: when watch mode is cleared by a timer a, irq 0 , or wkp 0 to wkp 7 interrupt request, the mode to which a transition is made depends on the settings of lson in syscr1 and mson in syscr2. if both lson and mson are cleared to 0, transition is to active (high-speed) mode; if lson = 0 and mson = 1, transition is to active (medium-speed) mode; if lson = 1, transition is to subactive mode. when the transition is to active mode, after the time set in syscr1 bits sts2 to sts0 has elapsed, a stable clock signal is supplied to the entire chip, watch mode is cleared, and interrupt exception handling starts. watch mode is not cleared if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. clearing by res input: clearing by res pin is the same as for standby mode; see 5.3.2, clearing standby mode. 5.4.3 oscillator settling time after watch mode is cleared the waiting time is the same as for standby mode; see 5.3.3, oscillator settling time after standby mode is cleared. 96 5.5 subsleep mode 5.5.1 transition to subsleep mode the system goes from subactive mode to subsleep mode when a sleep instruction is executed while the ssby bit in syscr1 is cleared to 0, lson is set to 1, and bit tma3 in tma is set to?. in subsleep mode, operation of on-chip peripheral modules other than timer a and timer g is halted. as long as a minimum required voltage is applied, the contents of cpu registers and some registers of the on-chip peripheral modules*, and the on-chip ram contents, are retained. i/o ports keep the same states as before the transition. note: * the contents of sci3, dtmf generator registers are reset. 5.5.2 clearing subsleep mode subsleep mode is cleared by an interrupt (timer a, timer g, irq 0 to irq 4 , wkp 0 to wkp 7 ) or by a low input at the res pin. clearing by interrupt: when an interrupt is requested, subsleep mode is cleared and interrupt exception handling starts. subsleep mode is not cleared if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. clearing by res input: clearing by res input is the same as for standby mode; see 5.3.2, clearing standby mode. 97 5.6 subactive mode 5.6.1 transition to subactive mode subactive mode is entered from watch mode if a timer a, irq 0 , or wkp 0 to wkp 7 interrupt is requested while the lson bit in syscr1 is set to 1. from subsleep mode, subactive mode is entered if a timer a, timer g, irq 0 to irq 4 , or wkp 0 to wkp 7 interrupt is requested. a transition to subactive mode does not take place if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. the contents of sci3, dtmf generator registers are reset. 5.6.2 clearing subactive mode subactive mode is cleared by a sleep instruction or by a low input at the res pin. clearing by sleep instruction: if a sleep instruction is executed while the ssby bit in syscr1 is set to 1 and bit tma3 in tma is set to 1, subactive mode is cleared and watch mode is entered. if a sleep instruction is executed while ssby = 0 and lson = 1 in syscr1 and tma3 = 1 in tma, subsleep mode is entered. direct transfer to active mode is also possible; see 5.8, direct transfer, below. clearing by res pin: clearing by res pin is the same as for standby mode; see 5.3.2, clearing standby mode. 5.6.3 operating frequency in subactive mode the operating frequency in subactive mode is set in bits sa1 and sa0 in syscr2. the choices are w /2, w /4, and w /8. 98 5.7 active (medium-speed) mode 5.7.1 transition to active (medium-speed) mode if the mson bit in syscr2 is set to 1 while the lson bit in syscr1 is cleared to 0, a transition to active (medium-speed) mode results from irq 0 , irq 1 , or wkp 0 to wkp 7 interrupts in standby mode, timer a, irq 0 , or wkp 0 to wkp 7 interrupts in watch mode, or any interrupt in sleep mode. a transition to active (medium-speed) mode does not take place if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. 5.7.2 clearing active (medium-speed) mode active (medium-speed) mode is cleared by a sleep instruction or by a low input at the reset. clearing by sleep instruction: a transition to standby mode takes place if a sleep instruction is executed while the ssby bit in syscr1 is set to 1, the lson bit in syscr1 is cleared to 0, and bit tma3 in tma is cleared to 0. the system goes to watch mode if the ssby bit in syscr1 is set to 1 and bit tma3 in tma is set to 1 when a sleep instruction is executed. sleep mode is entered if both ssby and lson are cleared to 0 when a sleep instruction is executed. direct transfer to active (high-speed) mode or to subactive mode is also possible. see 5.8, direct transfer, below for details. clearing by reset: when the res pin goes low, the cpu goes into the reset state and active (medium-speed) mode is cleared. 5.7.3 operating frequency in active (medium-speed) mode in active (medium-speed) mode, the cpu is clocked at 1/8 the frequency in active (high-speed) mode. the dtmf generator, however, continues to operate on the osc clock ( osc ). 99 5.8 direct transfer 5.8.1 overview the cpu can execute programs in three modes: active (high-speed) mode, active (medium-speed) mode, and subactive mode. a direct transfer is a transition among these three modes without the stopping of program execution. a direct transfer can be made by executing a sleep instruction while the dton bit in syscr2 is set to 1. after the mode transition, direct transfer interrupt exception handling starts. if the direct transfer interrupt is disabled in interrupt enable register 2 (ienr2), a transition is made instead to sleep mode or watch mode. note that if a direct transition is attempted while the i bit in ccr is set to 1, sleep mode or watch mode will be entered, and it will be impossible to clear the resulting mode by means of an interrupt. direct transfer from active (high-speed) mode to active (medium-speed) mode: when a sleep instruction is executed in active (high-speed) mode while the ssby and lson bits in syscr1 are cleared to 0, the mson bit in syscr2 is set to 1, and the dton bit in syscr2 is set to 1, a transition is made to active (medium-speed) mode via sleep mode. direct transfer from active (high-speed) mode to active (high-speed) mode: when a sleep instruction is executed in active (medium-speed) mode while the ssby and lson bits in syscr1 are cleared to 0, the mson bit in syscr2 is cleared to 0, and the dton bit in syscr2 is set to 1, a transition is made to active (high-speed) mode via sleep mode. direct transfer from active (high-speed) mode to subactive mode: when a sleep instruction is executed in active (high-speed) mode while the ssby and lson bits in syscr1 are set to 1, the dton bit in syscr2 is set to 1, and bit tma3 in tma is set to 1, a transition is made to subactive mode via watch mode. direct transfer from subactive mode to active (high-speed) mode: when a sleep instruction is executed in subactive mode while the ssby bit in syscr1 is set to 1, the lson bit in syscr1 is cleared to 0, the mson bit in syscr2 is cleared to 0, the dton bit in syscr2 is set to 1, and bit tma3 in tma is set to 1, a transition is made directly to active (high-speed) mode via watch mode after the waiting time set in syscr1 bits sts2 to sts0 has elapsed. direct transfer from active (medium-speed) mode to subactive mode: when a sleep instruction is executed in active (medium-speed) mode while the ssby and lson bits in syscr1 are set to 1, the dton bit in syscr2 is set to 1, and bit tma3 in tma is set to 1, a transition is made to subactive mode via watch mode. direct transfer from subactive mode to active (medium-speed) mode: when a sleep instruction is executed in subactive mode while the ssby bit in syscr1 is set to 1, the lson bit in syscr1 is cleared to 0, the mson bit in syscr2 is set to 1, the dton bit in syscr2 is set 100 to 1, and bit tma3 in tma is set to 1, a transition is made directly to active (medium-speed) mode via watch mode after the waiting time set in syscr1 bits sts2 to sts0 has elapsed. 5.8.2 direct transfer time time for direct transfer from active (high-speed) mode to active (medium-speed) mode: when a sleep instruction is executed in active (high-speed) mode while the ssby bit in syscr1 is cleared to 0, the lson bit in syscr1 is cleared to 0, the mson bit in syscr2 is set to 1, and the dton bit in syscr2 is set to 1, a transition is made directly to active (medium-speed) mode. in this case, the time from execution of the sleep instruction to the end of interrupt exception handling (the direct transfer time) is given by equation (1) below: direct transfer time ={ (number of sleep instruction execution states) + (number of internal processing states) } (t cyc before transition) + (number of interrupt exception handling execution states) (t cyc after transition) ...................................................................... (1) example: h8/3627 series direct transfer time = (2 + 1) 2t osc + 14 16t osc = 230t osc legend: t osc : osc clock cycle time t cyc : system clock (?) cycle time time for direct transfer from active (medium-speed) mode to active (high-speed) mode: when a sleep instruction is executed in active (medium-speed) mode while the ssby bit in syscr1 is cleared to 0, the lson bit in syscr1 is cleared to 0, the mson bit in syscr2 is cleared to 0, and the dton bit in syscr2 is set to 1, a transition is made directly to active (high-speed) mode. in this case, the time from execution of the sleep instruction to the end of interrupt exception handling (the direct transfer time) is given by equation (2) below: direct transfer time ={ (number of sleep instruction execution states) + (number of internal processing states) } (t cyc before transition) + (number of interrupt exception handling execution states) (t cyc after transition) ...................................................................... (2) example: h8/3627 series direct transfer time = (2 + 1) 16t osc + 14 2t osc = 76t osc legend: t osc : osc clock cycle time t cyc : system clock (?) cycle time 101 time for direct transfer from subactive mode to active (high-speed) mode: when a sleep instruction is executed in subactive mode while the ssby bit in syscr1 is set to 1, the lson bit in syscr1 is cleared to 0, the mson bit in syscr2 is cleared to 0, the dton bit in syscr2 is set to 1, and bit tma3 in tma is set to 1, a transition is made directly to active (high-speed) mode. in this case, the time from execution of the sleep instruction to the end of interrupt exception handling (the direct transfer time) is given by equation (3) below: direct transfer time ={ (number of sleep instruction execution states) + (number of internal processing states) } (t subcyc before transition) + { (standby time set in sts2 to sts0) + (number of interrupt exception handling execution states) } (t cyc after transition) ...................................................................... (3) example: h8/3627 series direct transfer time = (2 + 1) 8t w + (8192 + 14) 2t osc = 24t w + 16412t osc (when ? w /8 cpu operating clock and 8192-state standby time are selected) legend: t osc : osc clock cycle time t w : watch clock cycle time t cyc : system clock (?) cycle time t subcyc : subclock (? sub ) cycle time time for direct transfer from subactive mode to active (medium-speed) mode: when a sleep instruction is executed in subactive mode while the ssby bit in syscr1 is set to 1, the lson bit in syscr1 is cleared to 0, the mson bit in syscr2 is set to 1, the dton bit in syscr2 is set to 1, and bit tma3 in tma is set to 1, a transition is made directly to active (medium-speed) mode. in this case, the time from execution of the sleep instruction to the end of interrupt exception handling (the direct transfer time) is given by equation (4) below: direct transfer time ={ (number of sleep instruction execution states) + (number of internal processing states) } (t subcyc before transition) + { (standby time set in sts2 to sts0) + (number of interrupt exception handling execution states) } (t cyc after transition) ...................................................................... (4) example: h8/3627 series direct transfer time = (2 + 1) 8t w + (8192 + 14) 16t osc = 24t w + 13129t osc (when ? w /8 cpu operating clock and 8192-state standby time are selected) legend: t osc : osc clock cycle time t w : watch clock cycle time t cyc : system clock (?) cycle time t subcyc : subclock (? sub ) cycle time 102 103 section 6 rom 6.1 overview the h8/3627 has 60 kbytes of on-chip mask rom, while the h8/3626 has 48 kbytes the h8/3625 has 40 kbytes the h8/3624s has 32 kbytes the h8/3623s has 24 kbytes and the h8/3622s has 16 kbytes. the h8/3627 also has 60 kbytes of on-chip prom. the rom is connected to the cpu by a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data. 6.1.1 block diagram figure 6.1 shows a block diagram of the on-chip rom. internal data bus (upper 8 bits) internal data bus (lower 8 bits) even-numbered address odd-numbered address h'0002 h'0000 h'0000 h'0002 h'0001 h'0003 on-chip rom h'edfe h'edff h'edfe figure 6.1 rom block diagram (h8/3627) 104 6.2 prom mode 6.2.1 selection of prom mode if the on-chip rom is prom, setting the chip to prom mode stops operation as a microcomputer and allows the on-chip prom to be programmed in the same way as the hn27c101, except that page programming is not supported. table 6.1 shows how to set prom mode. table 6.1 setting prom mode pin name setting test high level pb 7 /an 7 low level pb 6 /an 6 6.2.2 socket adapter pin arrangement and memory map a standard prom programmer can be used to program the prom. a socket adapter is required for conversion to 32 pins. figure 6.2 shows the pin-to-pin wiring of the socket adapter. figure 6.3 shows a memory map. 105 h8/3627 eprom socket res p6 0 p6 1 p6 2 p6 3 p6 4 p6 5 p6 6 p6 7 p8 7 p8 6 p8 5 p8 4 p8 3 p8 2 p8 1 p8 0 p7 0 p2 p7 2 7 p7 3 p7 4 p7 5 p7 6 p1 4 p1 5 v cc cv cc test x 1 p1 1 p1 2 p1 6 v ss pb 7 pb 6 hn27c101 (32 pins) 1 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22 24 31 32 fp-64a fp-64e 8 36 37 38 39 40 41 42 43 59 58 57 56 55 54 53 52 44 16 46 47 48 49 50 20 19 51 45 21 7 64 6 1 23 22 18 3 62 63 pin v pp eo 0 eo 1 eo 2 eo 3 eo 4 eo 5 eo 6 eo 7 ea 0 ea 1 ea 2 ea 3 ea 4 ea 5 ea 6 ea 7 ea 8 ea 9 ea 10 ea 11 ea 12 ea 13 ea 14 ce oe pgm v cc v ss note: pins not indicated in the figure should be left open. p7 7 p7 1 p1 3 ea 15 ea 16 pin 16 figure 6.2 socket adapter pin correspondence 106 on-chip prom unused area h'0000 h'edff h'0000 h'edff h'1ffff address in mcu mode address in prom mode * note: * unpredictable data may be output if this area is read in prom mode. when programming with a prom programmer, be sure to specify addresses from h'0000 to h'edff. if h'ee00 and higher addresses are programmed by mistake, it may become impossible to program or verify the prom. when programming, specify h'ff for this address area (h'ee00 to h'1ffff). figure 6.3 memory map in prom mode 107 6.3 programming the program, verify, and other modes are selected as shown in table 6.2 in prom mode. table 6.2 mode selection in prom mode pin mode ce oe pgm v pp v cc eo 7 to eo 0 ea 16 to ea 0 write l h l v pp v cc data input address input verify l l h v pp v cc data output address input programming lllv pp v cc high impedance address input disabled lhh hl l hhh legend: l: low level h: high level v pp :v pp level v cc :v cc level the programming and verifying specifications in prom mode are the same as the specifications of the standard hn27c101 eprom. page programming is not supported, however. the prom programmer must not be set to page mode. prom programmers that support only page programming cannot be used. when selecting a prom programmer, make sure that it supports a byte-by-byte high-speed, high-reliability programming method. be sure to set the address range to h'0000 to h'edff. 108 6.3.1 programming and verification an efficient, high-speed, high-reliability programming procedure can be used to program and verify data. this procedure programs the chip quickly without subjecting it to voltage stress and without sacrificing data reliability. data in unused address areas is h'ff. figure 6.4 shows the basic high-speed, high-reliability programming flow chart. start set program/verify mode v = 6.0 v 0.25 v, v = 12.5 v 0.3 v cc pp address = 0 n = 0 n + 1 n program with t = 0.2 ms 5% ? pw verification ok? overprogram with t = 0.2n ms opw last address? set read mode v = 5.0 v 0.25 v, v = v cc pp cc all addresses read? end fail n 25 < address + 1 address ? no yes no yes yes no no yes figure 6.4 high-speed, high-reliability programming flow chart 109 table 6.3 and table 6.4 give the electrical characteristics in programming mode. table 6.3 dc characteristics (conditions: v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, v ss = 0 v, t a = 25 c 5 c) item symbol min typ max unit test condition input high- level voltage eo 7 to eo 0 , ea 16 to ea 0 oe , ce , pgm v ih 2.4 v cc + 0.3 v input low- level voltage eo 7 to eo 0 , ea 16 to ea 0 oe , ce , pgm v il ?.3 0.8 v output high- level voltage eo 7 to eo 0 v oh 2.4 v i oh = ?00 m a output low- level voltage eo 7 to eo 0 v ol 0.45 v i ol = 0.8 ma input leakage current eo 7 to eo 0 , ea 16 to ea 0 oe , ce , pgm |i li | 2 m av in = 5.25 v/ 0.5 v v cc current i cc 40 ma v pp current i pp 40 ma 110 table 6.4 ac characteristics (conditions: v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, t a = 25 c 5 c) item symbol min typ max unit test conditions address setup time t as 2 m s figure 6.5 * 1 oe setup time t oes 2 m s data setup time t ds 2 m s address hold time t ah 0 m s data hold time t dh 2 m s data output disable time t df * 2 130 ns v pp setup time t vps 2 m s programming pulse width t pw 0.19 0.20 0.21 ms pgm pulse width for over- programming t opw * 3 0.19 5.25 ms v cc setup time t vcs 2 m s ce setup time t ces 2 m s data output delay time t oe 0 200 ns notes: 1. input pulse level: 0.45 v to 2.4 v input rise time/fall time 20 ns timing reference levels: input: 0.8 v, 2.0 v output: 0.8 v, 2.0 v 2. t df is defined at the point at which the output is floating and the output level cannot be read. 3. t opw is defined by the value given in the hi-speed, hi-reliability programming flow chart in figure 6.4. 111 figure 6.5 shows a program/verify timing diagram. address data v pp v cc ce pgm oe v pp v cc v cc v cc program verify input data output data t as t ds t vps t vcs t ces t pw t opw * t dh t oes t oe t df t ah note: * t opw is defined by the value given in the high-speed, high-reliability programming flow chart in figure 6.4. +1 figure 6.5 prom program/verify timing 112 6.3.2 programming precautions use the specified programming voltage and timing. the programming voltage in prom mode (v pp ) is 12.5 v. use of a higher voltage can permanently damage the chip. be especially careful with respect to prom programmer overshoot. setting the prom programmer to hitachi specifications for the hn27c101 will result in correct v pp of 12.5 v. make sure the index marks on the prom programmer socket, socket adapter, and chip are properly aligned. if they are not, the chip may be destroyed by excessive current flow. before programming, be sure that the chip is properly mounted in the prom programmer. avoid touching the socket adapter or chip while programming, since this may cause contact faults and write errors. select the programming mode carefully. the chip cannot be programmed in page programming mode. when programming with a prom programmer, be sure to specify addresses from h'0000 to h'edff. if address h'ee00 and higher addresses are programmed by mistake, it may become impossible to program the prom or verify the programmed data. when programming, assign h'ff data to the address area from h'ee00 to h'1ffff. 113 6.4 reliability of programmed data a highly effective way of assuring data retention characteristics after programming is to screen the chips by baking them at a temperature of 150 c. this quickly eliminates prom memory cells causing initial data retention failure. figure 6.6 shows a flowchart of this screening procedure. install write program and verify contents bake at high temperature with power off 125 c to 150 c, 24 hrs to 48 hrs read and check program figure 6.6 recommended screening procedure if write errors occur repeatedly while the same prom programmer is being used, stop programming and check for problems in the prom programmer and socket adapter, etc. please notify your hitachi representative of any problems occurring during programming or in screening after high-temperature baking. 114 115 section 7 ram 7.1 overview the h8/3627 series has 1 kbyte or 2 kbytes of high-speed static ram on-chip. the ram is connected to the cpu by a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data. 7.1.1 block diagram figure 7.1 shows a block diagram of the on-chip ram. h'ff7e h'ff7f internal data bus (upper 8 bits) internal data bus (lower 8 bits) even-numbered address odd-numbered address h'ff7e h'f782 h'f780 h'f780 h'f782 h'f781 h'f783 on-chip ram figure 7.1 ram block diagram (example of 2 kbytes ram) 116 117 section 8 i/o ports 8.1 overview the h8/3627 series is provided with five 8-bit i/o ports, one 7-bit i/o port, one 3-bit i/o port, one 2-bit input-only port, and one 1-bit input-only port. table 8.1 indicates the functions of each port. each port has of a port control register (pcr) that controls input and output, and a port data register (pdr) for storing output data. input or output can be controlled by individual bits. see 2.9.2, notes on bit manipulation, for information on executing bit-manipulation instructions to write data in pcr or pdr. block diagrams of each port are given in appendix c, i/o port block diagrams. 118 table 8.1 port functions port description pins other functions function switching register port 1 8-bit i/o port input pull-up mos option p1 7 to p1 5 / irq 3 to irq 1 / tmif external interrupts 3 to 1 timer event input tmif pmr1 tcrf p1 4 none p1 3 /tmig timer g input capture pmr1 p1 2 , p1 1 /tmofh, tmofl timer f output compare pmr1 p1 0 /tmow timer a clock output pmr1 port 2 1-bit input-only port p2 7 external interrupt 0 pmr2 7-bit i/o port input pull-up mos option p2 6 /txd p2 5 /rxd p2 4 /sck 3 sci3 data output (txd), data input (rxd), clock input/output (sck 3 ) scr3 smr3 pmr6 p2 3 /so 1 p2 2 /si 1 p2 1 /sck 1 sci1 data output (so 1 ), data input (si 1 ), clock input/output (sck 1 ) pmr2 p2 0 / irq 4 / adtrg external interrupt 4 and a/d converter external trigger pmr2 port 5 8-bit i/o port input pull-up mos option p5 7 to p5 0 / wkp 7 to wkp 0 wakeup input ( wkp 7 to wkp 0 ) pmr5 port 6 8-bit i/o port input pull-up mos option p6 7 to p6 0 none port 7 8-bit i/o port p7 7 to p7 0 none port 8 8-bit i/o port p8 7 to p8 0 none port a 3-bit i/o port pa 3 to pa 1 none port b 2-bit input port pb 7 , pb 6 /an 7 , an 6 a/d converter analog input amr 119 8.2 port 1 8.2.1 overview port 1 is an 8-bit i/o port. figure 8.1 shows its pin configuration. p1 7 / irq 3 /tmif p1 6 / irq 2 p1 5 / irq 1 p1 4 p1 3 /tmig p1 2 /tmofh p1 1 /tmofl p1 0 /tmow port 1 figure 8.1 port 1 pin configuration 8.2.2 register configuration and description table 8.2 shows the port 1 register configuration. table 8.2 port 1 registers name abbrev. r/w initial value address port data register 1 pdr1 r/w h'00 h'ffd4 port control register 1 pcr1 w h'00 h'ffe4 port pull-up control register 1 pucr1 r/w h'00 h'ff9c port mode register 1 pmr1 r/w h'00 h'ff98 120 port data register 1 (pdr1) bit 76543210 p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pdr1 is an 8-bit register that stores data for pins p1 7 to p1 0 of port 1. if port 1 is read while pcr1 bits are set to 1, the values stored in pdr1 are directly read, regardless of the actual pin states. if port 1 is read while pcr1 bits are cleared to 0, the pin states are read. upon reset, pdr1 is initialized to h'00. port control register 1 (pcr1) bit 76543210 pcr1 7 pcr1 6 pcr1 5 pcr1 4 pcr1 3 pcr1 2 pcr1 1 pcr1 0 initial value 00000000 read/write wwwwwwww pcr1 is an 8-bit register for controlling whether each of the port 1 pins p1 7 to p1 0 functions as an input pin or output pin. setting a pcr1 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. the settings in pcr1 and in pdr1 are valid only when the corresponding pin is designated in pmr1 as a general i/o pin. upon reset, pcr1 is initialized to h'00. pcr1 is a write-only register. all bits are read as 1. port pull-up control register 1 (pucr1) bit 76543210 pucr1 7 pucr1 6 pucr1 5 pucr1 4 pucr1 3 pucr1 2 pucr1 1 pucr1 0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pucr1 controls whether the mos pull-up of each port 1 pins p1 7 to p1 0 is on or off. when a pcr1 bit is cleared to 0, setting the corresponding pucr1 bit to 1 turns on the mos pull-up for the corresponding pin, while clearing the bit to 0 turns off the mos pull-up. upon reset, pucr1 is initialized to h'00. 121 port mode register 1 (pmr1) bit 76543210 irq3 irq2 irq1 tmig tmofh tmofl tmow initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w pmr1 is an 8-bit read/write register, controlling the selection of pin functions for port 1 pins. upon reset, pmr1 is initialized to h'00. bit 7?1 7 / irq 3 /tmif pin function switch (irq3): this bit selects whether pin p1 7 / irq 3 /tmif is used as p1 7 or as irq 3 /tmif. bit 7: irq3 description 0 functions as p1 7 i/o pin (initial value) 1 functions as irq 3 /tmif input pin note: rising or falling edge sensing can be designated for irq 3 /tmif. for information about tmif pin settings, see 9.3.2 (3), timer control register f (tcrf). bit 6?1 6 / irq 2 pin function switch (irq2): this bit selects whether pin p1 6 / irq 2 is used as p1 6 or as irq 2 . bit 6: irq2 description 0 functions as p1 6 i/o pin (initial value) 1 functions as irq 2 input pin note: rising or falling edge sensing can be designated for irq 2 . bit 5?1 5 / irq 1 pin function switch (irq1): this bit selects whether pin p1 5 / irq 1 is used as p1 5 or as irq 1 . bit 5: irq1 description 0 functions as p1 5 i/o pin (initial value) 1 functions as irq 1 input pin note: rising or falling edge sensing can be designated for irq 1 . bit 4?eserved bit: bit 4 is reserved: it is a always read as 0, and should be used cleared to 0. 122 bit 3?1 3 /tmig pin function switch (tmig): this bit selects whether pin p1 3 /tmig is used as p1 3 or as tmig. bit 3: tmig description 0 functions as p1 3 i/o pin (initial value) 1 functions as tmig input pin bit 2?1 2 /tmofh pin function switch (tmofh): this bit selects whether pin p1 2 /tmofh is used as p1 2 or as tmofh. bit 2: tmofh description 0 functions as p1 2 i/o pin (initial value) 1 functions as tmofh output pin bit 1?1 1 /tmofl pin function switch (tmofl): this bit selects whether pin p1 1 /tmofl is used as p1 1 or as tmofl. bit 1: tmofl description 0 functions as p1 1 i/o pin (initial value) 1 functions as tmofl output pin bit 0?1 0 /tmow pin function switch (tmow): this bit selects whether pin p1 0 /tmow is used as p1 0 or as tmow. bit 0: tmow description 0 functions as p1 0 i/o pin (initial value) 1 functions as tmow output pin 123 8.2.3 pin functions table 8.3 shows the port 1 pin functions. table 8.3 port 1 pin functions pin pin functions and selection method p1 7 / irq 3 /tmif the pin function depends on bit irq3 in pmr1, bits cksl2 to cksl0 in tcrf, and bit pcr1 7 in pcr1. irq3 0 1 pcr1 7 01 * cksl2 to cksl0 * not 0 ** 0 ** pin function p1 7 input pin p1 7 output pin irq 3 input pin irq 3 /tmif input pin note: when using this pin for tmif input, clear bit ien3 to 0 in ienr1 to disable irq 3 interrupts. p1 6 / irq 2 the pin function depends on bit irq2 in pmr1, bit pcr1 6 in pcr1. irq2 0 1 pcr1 6 01 * pin function p1 6 input pin p1 6 output pin irq 2 input pin p1 5 / irq 1 the pin function depends on bit irq1 in pmr1 and bit pcr1 5 in pcr1. irq1 0 1 pcr1 5 01 * pin function p1 5 input pin p1 5 output pin irq 1 input pin p1 4 the pin function depends on bit pcr1 4 in pcr1. pcr1 4 01 pin function p1 4 input pin p1 4 output pin p1 3 /tmig the pin function depends on bit tmig in pmr1 and bit pcr1 3 in pcr1. tmig 0 1 pcr1 3 01 * pin function p1 3 input pin p1 3 output pin tmig input pin 124 table 8.3 port 1 pin functions (cont) pin pin functions and selection method p1 2 /tmofh the pin function depends on bit tmofh in pmr1 and bit pcr1 2 in pcr1. tmofh 0 1 pcr1 2 01 * pin function p1 2 input pin p1 2 output pin tmofh output pin p1 1 /tmofl the pin function depends on bit tmofl in pmr1 and bit pcr1 1 in pcr1. tmofl 0 1 pcr1 1 01 * pin function p1 1 input pin p1 1 output pin tmofl output pin p1 0 /tmow the pin function depends on bit tmow in pmr1 and bit pcr1 0 in pcr1. tmow 0 1 pcr1 0 01 * pin function p1 0 input pin p1 0 output pin tmow output pin note: * don? care 8.2.4 pin states table 8.4 shows the port 1 pin states in each operating mode. table 8.4 port 1 pin states pins reset sleep subsleep standby watch subactive active p1 7 / irq 3 /tmif p1 6 / irq 2 p1 5 / irq 1 p1 4 p1 3 /tmig p1 2 /tmofh p1 1 /tmofl p1 0 /tmow high- impedance retains previous state retains previous state high- impedance * retains previous state functional functional note: * a high-level signal is output when the mos pull-up is in the on state. 125 8.2.5 mos input pull-up port 1 has a built-in mos input pull-up function that can be controlled by software. when a pcr1 bit is cleared to 0, setting the corresponding pucr1 bit to 1 turns on the mos pull-up for that pin. the mos input pull-up function is in the off state after a reset. pcr1 n 01 pucr1 n 01 * mos input pull-up off on off note: * don? care (n = 7 to 0) 126 8.3 port 2 8.3.1 overview port 2 is an 7-bit i/o port and 1-bit input port. figure 8.2 shows its pin configuration. p2 7 / irq 0 p2 6 /txd p2 5 /rxd p2 4 /sck 3 p2 3 /so 1 p2 2 /si 1 p2 1 /sck 1 p2 0 / irq 4 / adtr g port 2 figure 8.2 port 2 pin configuration 8.3.2 register configuration and description table 8.5 shows the port 2 register configuration. table 8.5 port 2 registers name abbrev. r/w initial value address port data register 2 pdr2 r/w h'00 h'ffd5 port control register 2 pcr2 w h'00 h'ffe5 port mode register 2 pmr2 r/w h'40 h'ff99 port mode register 6 pmr6 r/w h'f8 h'ff9a port pull-up control register 2 pucr2 r/w h'00 h'ff9d 127 port data register 2 (pdr2) bit 76543210 p2 7 p2 6 p2 5 p2 4 p2 3 p2 2 p2 1 p2 0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pdr2 is an 8-bit register that stores data for pins p2 7 to p2 0 of port 2. if port 2 is read while pcr2 bits are set to 1, the values stored in pdr2 are directly read, regardless of the actual pin states. if port 2 is read while pcr2 bits are cleared to 0, the pin states are read. upon reset, pdr2 is initialized to h'00. port control register 2 (pcr2) bit 76543210 pcr2 7 pcr2 6 pcr2 5 pcr2 4 pcr2 3 pcr2 2 pcr2 1 pcr2 0 initial value 00000000 read/write wwwwwwww pcr2 is an 8-bit register for controlling whether each of the port 2 pins p2 7 to p2 0 functions as an input pin or output pin. setting a pcr2 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. the settings in pcr2 and in pdr2 are valid only when the corresponding pin is designated in pmr2 as a general i/o pin. upon reset, pcr2 is initialized to h'00. pcr2 is a write-only register, which always reads all 1s. note: as p2 7 is an input-only pin, it becomes a high-impedance output when pcr2 7 is set to 1. 128 port mode register 2 (pmr2) bit 76543210 irq0 pof1 ncs so1 si1 sck1 irq4 initial value 01000000 read/write r/w r/w r/w r/w r/w r/w r/w pmr2 is an 8-bit read/write register for controlling the selection of pin functions for pins p2 0 to p2 3 and p2 7 , controlling the pmos on/off option for pin p2 3 /so 1 , and controlling the tmig input noise canceller. upon reset, pmr2 is initialized to h'40. bits 7?2 7 / irq 0 pin function switch (irq0): this bit selects whether pin p2 7 / irq 0 is used as p2 7 or as irq 0 . bit 7: irq0 description 0 functions as p2 7 input pin (initial value) 1 functions as irq 0 input pin bit 6?eserved bit: bit 6 is reserved: it is always read as 1, and cannot be modified. bit 5?2 3 /so 1 pin pmos control (pof1): this bit turns on and off the pmos transistor in the p2 3 /so 1 pin output buffer. bit 5: pof1 description 0 cmos output (initial value) 1 nmos open-drain output bit 4?mig noise canceller select (ncs): this bit controls the noise canceller circuit for input capture at pin tmig. bit 4: ncs description 0 noise canceller function not selected (initial value) 1 noise canceller function selected 129 bit 3?2 3 /so 1 pin function switch (so1): this bit selects whether pin p2 3 /so 1 is used as p2 3 or as so 1 . bit 3: so1 description 0 functions as p2 3 i/o pin (initial value) 1 functions as so 1 output pin bit 2?2 2 /si 1 pin function switch (si1): this bit selects whether pin p2 2 /si 1 is used as p2 2 or as si 1 . bit 2: si1 description 0 functions as p2 2 i/o pin (initial value) 1 functions as si 1 input pin bit 1?2 1 /sck 1 pin function switch (sck1): this bit selects whether pin p2 1 /sck 1 is used as p2 1 or as sck 1 . bit 1: sck1 description 0 functions as p2 1 i/o pin (initial value) 1 functions as sck 1 i/o pin bit 0?2 0 / irq 4 / adtrg pin function switch (irq4): this bit selects whether pin p2 0 / irq 4 / adtrg is used as p2 0 or as irq 4 / adtrg . bit 0: irq4 description 0 functions as p2 0 i/o pin (initial value) 1 functions as irq 4 / adtrg input pin note: for information about adtrg pin settings, see 12.3.2, start of a/d conversion by external trigger input. 130 port mode register 6 (pmr6) bit 76543210 txd initial value 11111000 read/write r/w r/w r/w r/w r/w bits 7, 6, and 3: reserved bits: bits 7, 6, and 3 are reserved bits. they are always read as 1 and cannot be modified. bit 5, 4?eserved bit: bit 5, 4 is reserved: it should be used set to 1. bit 2?2 6 /txd pin function switch (txd): this bits selects whether the p2 6 /txd pin is used as p2 6 or as txd. bit 2: txd description 0 functions as p2 6 i/o pin (initial value) 1 functions as txd output pin bits 1 and 0?eserved bits: bits 1 and 0 are reserved: they should be used cleared to 0. port pull-up control register 2 (pucr2) bit 76543210 pucr2 7 pucr2 6 pucr2 5 pucr2 4 pucr2 3 pucr2 2 pucr2 1 pucr2 0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pucr2 controls whether the mos pull-up of each port 2 pin is on or off. when a pcr2 bit is cleared to 0, setting the corresponding pucr2 bit to 1 turns on the mos pull-up for the corresponding pin, while clearing the bit to 0 turns off the mos pull-up. upon reset, pucr2 is initialized to h'00. note: as p2 7 is an input-only pin, the mos pull-up is turned off regardless of whether pucr2 7 is set to 1 or cleared to 0. 131 8.3.3 pin functions table 8.6 shows the port 2 pin functions. table 8.6 port 2 pin functions pin pin functions and selection method p2 7 / irq 0 the pin function depends on bit irq0 in pmr2 and bit pcr2 7 in pcr2. irq0 0 1 pcr2 7 01 * pin function p2 7 input pin high- impedance irq 0 input pin p2 6 /txd the pin function depends on bit txd in pmr6 and bit pcr2 6 in pcr2. txd 0 1 pcr2 6 01 * pin function p2 6 input pin p2 6 output pin txd output pin p2 5 /rxd the pin function depends on bit re in scr of sci3 and bit pcr2 5 in pcr2. re 0 1 pcr2 5 01 * pin function p2 5 input pin p2 5 output pin rxd input pin p2 4 /sck 3 the pin function depends on bits cke1 and cke0 in scr of sci3, bit com in smr of sci3, and bit pcr2 4 in pcr2. cke1 0 1 cke0 0 0 1 * com 0 1 ** pcr2 4 01 ** pin function p2 4 input pin p2 4 output pin sck 3 output pin sck 3 input pin p2 3 /so 1 the pin function depends on bit so1 in pmr2 and bit pcr2 3 in pcr2. so1 0 1 pcr2 3 01 * pin function p2 3 input pin p2 3 output pin so 1 output pin 132 table 8.6 port 2 pin functions (cont) pin pin functions and selection method p2 2 /si 1 the pin function depends on bit si1 in pmr2 and bit pcr2 2 in pcr2. si1 0 1 pcr2 2 01 * pin function p2 2 input pin p2 2 output pin si 1 input pin p2 1 /sck 1 the pin function depends on bit sck1 in pmr2, bit cks3 in scr1, and bit pcr2 1 in pcr2. sck1 0 1 cks 3 * 01 pcr2 1 01 ** pin function p2 1 input pin p2 1 output pin sck 1 output pin sck 1 input pin p2 0 / irq 4 / adtrg the pin function depends on bit irq4 in pmr2, bit trge in amr, and bit pcr2 0 in pcr2. irq4 0 1 pcr2 0 01 * trge * 01 pin function p2 0 input pin p2 0 output pin irq 4 input pin irq 4 / adtrg input pin note: when using this pin for adtrg input, clear bit ien4 to 0 in ienr1 to disable irq 4 interrupts. note: * don? care 133 8.3.4 pin states table 8.7 shows the port 2 pin states in each operating mode. table 8.7 port 2 pin states pins reset sleep subsleep standby watch subactive active p2 7 / irq 0 high- impedance high- impedance high- impedance high- impedance high- impedance high- impedance high- impedance p2 6 /txd p2 5 /rxd p2 4 /sck 3 p2 3 /so 1 p2 2 /si 1 p2 1 /sck 1 p2 0 / irq 4 / adtrg high- impedance retains previous state retains previous state high- impedance * retains previous state functional functional note: * high level output if the mos pull-up is on. 8.3.5 mos input pull-up port 2 has a built-in mos input pull-up function that can be controlled by software. when a pcr2 bit is cleared to 0, setting the corresponding pucr2 bit to 1 turns on the mos pull-up for that pin. the mos input pull-up function is in the off state after a reset. pcr2 n 01 pucr2 n 01 * mos input pull-up off on off note: * don? care (n = 6 to 0) note: as p2 7 is an input-only pin, the mos pull-up is turned off regardless of whether pucr2 7 is set to 1 or cleared to 0. 134 8.4 port 5 8.4.1 overview port 5 is an 8-bit i/o port, configured as shown in figure 8.3. p5 / wkp p5 / wkp p5 / wkp p5 / wkp p5 / wkp p5 / wkp p5 / wkp p5 / wkp 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 port 5 figure 8.3 port 5 pin configuration 8.4.2 register configuration and description table 8.8 shows the port 5 register configuration. table 8.8 port 5 registers name abbrev. r/w initial value address port data register 5 pdr5 r/w h'00 h'ffd8 port control register 5 pcr5 w h'00 h'ffe8 port pull-up control register 5 pucr5 r/w h'00 h'ff9e port mode register 5 pmr5 r/w h'00 h'ff9b 135 port data register 5 (pdr5) bit 76543210 p5 7 p5 6 p5 5 p5 4 p5 3 p5 2 p5 1 p5 0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pdr5 is an 8-bit register that stores data for port 5 pins p5 7 to p5 0 . if port 5 is read while pcr5 bits are set to 1, the values stored in pdr5 are directly read, regardless of the actual pin states. if port 5 is read while pcr5 bits are cleared to 0, the pin states are read. upon reset, pdr5 is initialized to h'00. port control register 5 (pcr5) bit 76543210 pcr5 7 pcr5 6 pcr5 5 pcr5 4 pcr5 3 pcr5 2 pcr5 1 pcr5 0 initial value 00000000 read/write wwwwwwww pcr5 is an 8-bit register for controlling whether each of the port 5 pins p5 7 to p5 0 functions as an input pin or output pin. setting a pcr5 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. the settings in pcr5 and in pdr5 are valid only when the corresponding pin is designated as a general i/o pin in pmr5. upon reset, pcr5 is initialized to h'00. pcr5 is a write-only register. all bits are read as 1. port pull-up control register 5 (pucr5) bit 76543210 pucr5 7 pucr5 6 pucr5 5 pucr5 4 pucr5 3 pucr5 2 pucr5 1 pucr5 0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pucr5 controls whether the mos pull-up of each port 5 pin is on or off. when a pcr5 bit is cleared to 0, setting the corresponding pucr5 bit to 1 turns on the mos pull-up for the corresponding pin, while clearing the bit to 0 turns off the mos pull-up. upon reset, pucr5 is initialized to h'00. 136 port mode register 5 (pmr5) bit 76543210 wkp 7 wkp 6 wkp 5 wkp 4 wkp 3 wkp 2 wkp 1 wkp 0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pmr5 is an 8-bit read/write register, controlling the selection of pin functions for port 5 pins. upon reset, pmr5 is initialized to h'00. bit n: p5 n / wkp n pin function switch (wkpn): this bit selects whether it is used as p5 n or as wkp n . bit n: wkpn description 0 functions as p5 n i/o pin (initial value) 1 functions as wkp n input pin (n = 7 to 0) 8.4.3 pin functions table 8.9 shows the port 5 pin functions. table 8.9 port 5 pin functions pin pin functions and selection method p5 7 / wkp 7 to p5 0 / wkp 0 the pin function depends on bit wkp n in pmr5 and bit pcr5 n in pcr5. (n = 7 to 0) wkp n 01 pcr5 n 01 * pin function p5 n input pin p5 n output pin wkp n input pin note: * don? care 137 8.4.4 pin states table 8.10 shows the port 5 pin states in each operating mode. table 8.10 port 5 pin states pins reset sleep subsleep standby watch subactive active p5 7 / wkp 7 to p5 0 / wkp 0 high- impedance retains previous state retains previous state high- impedance * retains previous state functional functional note: * a high-level signal is output when the mos pull-up is in the on state. 8.4.5 mos input pull-up port 5 has a built-in mos input pull-up function that can be controlled by software. when a pcr5 bit is cleared to 0, setting the corresponding pucr5 bit to 1 turns on the mos pull-up for that pin. the mos pull-up function is in the off state after a reset. pcr5 n 01 pucr5 n 01 * mos input pull-up off on off note: * don? care (n = 7 to 0) 138 8.5 port 6 8.5.1 overview port 6 is an 8-bit i/o port, configured as shown in figure 8.4. p6 p6 p6 p6 p6 p6 p6 p6 7 6 5 4 3 2 1 0 port 6 figure 8.4 port 6 pin configuration 8.5.2 register configuration and description table 8.11 shows the port 6 register configuration. table 8.11 port 6 registers name abbrev. r/w initial value address port data register 6 pdr6 r/w h'00 h'ffd9 port control register 6 pcr6 w h'00 h'ffe9 port pull-up control register 6 pucr6 r/w h'00 h'ff9f 139 port data register 6 (pdr6) bit 76543210 p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pdr6 is an 8-bit register that stores data for port 6 pins p6 7 to p6 0 . if port 6 is read while pcr6 bits are set to 1, the values stored in pdr6 are directly read, regardless of the actual pin states. if port 6 is read while pcr6 bits are cleared to 0, the pin states are read. upon reset, pdr6 is initialized to h'00. port control register 6 (pcr6) bit 76543210 pcr6 7 pcr6 6 pcr6 5 pcr6 4 pcr6 3 pcr6 2 pcr6 1 pcr6 0 initial value 00000000 read/write wwwwwwww pcr6 is an 8-bit register for controlling whether each of the port 6 pins p6 7 to p6 0 functions as an input pin or output pin. setting a pcr6 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. upon reset, pcr6 is initialized to h'00. pcr6 is a write-only register. all bits are read as 1. port pull-up control register 6 (pucr6) bit 76543210 pucr6 7 pucr6 6 pucr6 5 pucr6 4 pucr6 3 pucr6 2 pucr6 1 pucr6 0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pucr6 controls whether the mos pull-up of each port 6 pin is on or off. when a pcr6 bit is cleared to 0, setting the corresponding pucr6 bit to 1 turns on the mos pull-up for the corresponding pin, while clearing the bit to 0 turns off the mos pull-up. upon reset, pucr6 is initialized to h'00. 140 8.5.3 pin functions table 8.12 shows the port 6 pin functions. table 8.12 port 6 pin functions pin pin functions and selection method p6 7 to p6 0 the pin function depends on bit pcr6 n in pcr6. (n = 7 to 0) pcr6 n 01 pin function p6 n input pin p6 n output pin 8.5.4 pin states table 8.13 shows the port 6 pin states in each operating mode. table 8.13 port 6 pin states pins reset sleep subsleep standby watch subactive active p6 7 to p6 0 high- impedance retains previous state retains previous state high- impedance * retains previous state functional functional note: * a high-level signal is output when the mos pull-up is in the on state. 8.5.5 mos input pull-up port 6 has a built-in mos input pull-up function that can be controlled by software. when a pcr6 bit is cleared to 0, setting the corresponding pucr6 bit to 1 turns on the mos pull-up for that pin. the mos pull-up function is in the off state after a reset. pcr6 n 01 puc6 n 01 * mos input pull-up off on off note: * don? care (n = 7 to 0) 141 8.6 port 7 8.6.1 overview port 7 is an 8-bit i/o port, configured as shown in figure 8.5. p7 p7 p7 p7 p7 p7 p7 p7 7 6 5 4 3 2 1 0 port 7 figure 8.5 port 7 pin configuration 8.6.2 register configuration and description table 8.14 shows the port 7 register configuration. table 8.14 port 7 registers name abbrev. r/w initial value address port data register 7 pdr7 r/w h'00 h'ffda port control register 7 pcr7 w h'00 h'ffea 142 port data register 7 (pdr7) bit 76543210 p7 7 p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p7 0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pdr7 is an 8-bit register that stores data for port 7 pins p7 7 to p7 0 . if port 7 is read while pcr7 bits are set to 1, the values stored in pdr7 are directly read, regardless of the actual pin states. if port 7 is read while pcr7 bits are cleared to 0, the pin states are read. upon reset, pdr7 is initialized to h'00. port control register 7 (pcr7) bit 76543210 pcr7 7 pcr7 6 pcr7 5 pcr7 4 pcr7 3 pcr7 2 pcr7 1 pcr7 0 initial value 00000000 read/write wwwwwwww pcr7 is an 8-bit register for controlling whether each of the port 7 pins p7 7 to p7 0 functions as an input pin or output pin. setting a pcr7 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. upon reset, pcr7 is initialized to h'00. pcr7 is a write-only register. all bits are read as 1. 143 8.6.3 pin functions table 8.15 shows the port 7 pin functions. table 8.15 port 7 pin functions pin pin functions and selection method p7 7 to p7 0 the pin function depends on bit pcr7 n in pcr7. (n = 7 to 0) pcr7 n 01 pin function p7 n input pin p7 n output pin 8.6.4 pin states table 8.16 shows the port 7 pin states in each operating mode. table 8.16 port 7 pin states pins reset sleep subsleep standby watch subactive active p7 7 to p7 0 high- impedance retains previous state retains previous state high- impedance retains previous state functional functional 144 8.7 port 8 8.7.1 overview port 8 is an 8-bit i/o port configured as shown in figure 8.6. p8 p8 p8 p8 p8 p8 p8 p8 7 6 5 4 3 2 1 0 port 8 figure 8.6 port 8 pin configuration 8.7.2 register configuration and description table 8.17 shows the port 8 register configuration. table 8.17 port 8 registers name abbrev. r/w initial value address port data register 8 pdr8 r/w h'00 h'ffdb port control register 8 pcr8 w h'00 h'ffeb 145 port data register 8 (pdr8) bit 76543210 p8 7 p8 6 p8 5 p8 4 p8 3 p8 2 p8 1 p8 0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pdr8 is an 8-bit register that stores data for port 8 pins p8 7 to p8 0 . if port 8 is read while pcr8 bits are set to 1, the values stored in pdr8 are directly read, regardless of the actual pin states. if port 8 is read while pcr8 bits are cleared to 0, the pin states are read. upon reset, pdr8 is initialized to h'00. port control register 8 (pcr8) bit 76543210 pcr8 7 pcr8 6 pcr8 5 pcr8 4 pcr8 3 pcr8 2 pcr8 1 pcr8 0 initial value 00000000 read/write wwwwwwww pcr8 is an 8-bit register for controlling whether each of the port 8 pins p8 7 to p8 0 functions as an input or output pin. setting a pcr8 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. upon reset, pcr8 is initialized to h'00. pcr8 is a write-only register. all bits are read as 1. 146 8.7.3 pin functions table 8.18 gives the port 8 pin functions. table 8.18 port 8 pin functions pin pin functions and selection method p8 7 to p8 0 the pin function depends on bit pcr8 n in pcr8. (n = 7 to 0) pcr8 n 01 pin function p8 n input pin p8 n output pin 8.7.4 pin states table 8.19 shows the port 8 pin states in each operating mode. table 8.19 port 8 pin states pins reset sleep subsleep standby watch subactive active p8 7 to p8 0 high- impedance retains previous state retains previous state high- impedance retains previous state functional functional 147 8.8 port a 8.8.1 overview port a is a 3-bit i/o port configured as shown in figure 8.7. pa pa pa 3 2 1 port a figure 8.7 port a pin configuration 8.8.2 register configuration and description table 8.20 shows the port a register configuration. table 8.20 port a registers name abbrev. r/w initial value address port data register a pdra r/w h'f0 h'ffdd port control register a pcra w h'f1 h'ffed 148 port data register a (pdra) bit 76543210 pa 3 pa 2 pa 1 initial value 11110000 read/write r/wr/wr/w pdra is an 8-bit register that stores data for port a pins pa 3 to pa 1 . if port a is read while pcra bits are set to 1, the values stored in pdra are directly read, regardless of the actual pin states. if port a is read while pcra bits are cleared to 0, the pin states are read. upon reset, pdra is initialized to h'f0. port control register a (pcra) bit 76543210 pcra 3 pcra 2 pcra 1 initial value 11110001 read/write www pcra is an 8-bit register for controlling whether each of the port a pins pa 3 to pa 1 functions as an input or output pin. setting a pcra bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. upon reset, pcra is initialized to h'f1. pcra is a write-only register. all bits are read as 1. 149 8.8.3 pin functions table 8.21 gives the port a pin functions. table 8.21 port a pin functions pin pin functions and selection method pa 3 to pa 1 the pin function depends on bit pcra n in pcra. (n = 3 to 1) pcra n 01 pin function pa n input pin pa n output pin 8.8.4 pin states table 8.22 shows the port a pin states in each operating mode. table 8.22 port a pin states pins reset sleep subsleep standby watch subactive active pa 3 to pa 1 high- impedance retains previous state retains previous state high- impedance retains previous state functional functional 150 8.9 port b 8.9.1 overview port b is an 2-bit input-only port configured as shown in figure 8.8. pb /an pb /an 7 6 7 6 port b figure 8.8 port b pin configuration 8.9.2 register configuration and description table 8.23 shows the port b register configuration. table 8.23 port b register name abbrev. r/w address port data register b pdrb r h'ffde port data register b (pdrb) bit 76543210 pb 7 pb 6 read/write r r reading pdrb always gives the pin states. however, if a port b pin is selected as an analog input channel for the a/d converter by amr bits ch3 to ch0, that pin reads 0 regardless of the input voltage. 151 section 9 timers 9.1 overview the h8/3627 series provides three timers (timers a, f, and g) on-chip. table 9.1 outlines the functions of timers a, f, and g. table 9.1 timer functions name functions internal clock event input pin waveform output pin remarks timer a 8-bit timer interval timer ?8 to ?8192 (8 choices) time base w /128 (choice of 4 overflow periods) clock output ?4 to ?32, w /4 to w /32 (8 choices) tmow timer f 16-bit free-running timer event counter can be used as two independent 8-bit timers output compare ?2 to ?32 (4 choices) tmif tmofl tmofh timer g 8-bit timer input capture interval timer ?2 to ?64, w /2 (4 choices) tmig counter clear designation possible built-in noise canceller circuit for input capture 152 9.2 timer a 9.2.1 overview timer a is an 8-bit timer with interval timing and real-time clock time-base functions. the clock time-base function is available when a 32.768-khz crystal oscillator is connected. a clock signal divided from 32.768 khz or from the system clock can be output at the tmow pin. features: features of timer a are given below. choice of eight internal clock sources (?8192, ?4096, ?2048, ?512, ?256, ?128, ?32, ?8). choice of four overflow periods (1 s, 0.5 s, 0.25 s, 31.25 ms) when timer a is used as a clock time base (using a 32.768 khz crystal oscillator). an interrupt is requested when the counter overflows. any of eight clock signals can be output from pin tmow: 32.768 khz divided by 32, 16, 8, or 4 (1 khz, 2 khz, 4 khz, 8 khz), or the system clock divided by 32, 16, 8, or 4. block diagram: figure 9.1 shows a block diagram of timer a. psw internal data bus pss legend: tmow 1/4 tma tca ? /32 ? /16 ? /8 ? /4 w w w w ?32 ?16 ?8 ?4 ? /128 w ?8192, ?4096, ?2048, ?512, ?256, ?128, ?32, ?8 irrta 8 64 128 256 * * * * ? /4 w tma: tca: irrta: psw: pss: note: can be selected only when the prescaler w output (? /128) is used as the tca input clock. timer mode register a timer counter a timer a overflow interrupt request flag prescaler w prescaler s w w ? ? ? ? figure 9.1 block diagram of timer a 153 pin configuration: table 9.2 shows the timer a pin configuration. table 9.2 pin configuration name abbrev. i/o function clock output tmow output output of waveform generated by timer a output circuit register configuration: table 9.3 shows the register configuration of timer a. table 9.3 timer a registers name abbrev. r/w initial value address timer mode register a tma r/w h'10 h'ffb0 timer counter a tca r h'00 h'ffb1 9.2.2 register descriptions timer mode register a (tma) bit 76543210 tma7 tma6 tma5 tma3 tma2 tma1 tma0 initial value 00010000 read/write r/w r/w r/w r/w r/w r/w r/w tma is an 8-bit read/write register for selecting the prescaler, input clock, and output clock. upon reset, tma is initialized to h'10. bits 7 to 5?lock output select (tma7 to tma5): bits 7 to 5 choose which of eight clock signals is output at the tmow pin. the system clock divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. a 32.768 khz signal divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, and subactive mode. 154 bit 7: tma7 bit 6: tma6 bit 5: tma5 clock output 0 0 0 ?32 (initial value) 1 ?16 1 0 ?8 1 ?4 100 w /32 1 w /16 10 w /8 1 w /4 bit 4?eserved bit: bit 4 is reserved; it is always read as 1, and cannot be modified. bits 3 to 0?nternal clock select (tma3 to tma0): bits 3 to 0 select the clock input to tca. the selection is made as follows. description bit 3: tma3 bit 2: tma2 bit 1: tma1 bit 0: tma0 prescaler and divider ratio or overflow period function 0000 pss, ?8192 (initial value) interval timer 1 pss, ?4096 1 0 pss, ?2048 1 pss, ?512 1 0 0 pss, ?256 1 pss, ?128 1 0 pss, ?32 1 pss, ?8 1000 psw, 1 s clock time base 1 psw, 0.5 s 1 0 psw, 0.25 s 1 psw, 0.03125 s 1 0 0 psw and tca are reset 1 10 1 155 timer counter a (tca) bit 76543210 tca7 tca6 tca5 tca4 tca3 tca2 tca1 tca0 initial value 00000000 read/write rrrrrrrr tca is an 8-bit read-only up-counter, which is incremented by internal clock input. the clock source for input to this counter is selected by bits tma3 to tma0 in timer mode register a (tma). tca values can be read by the cpu in active mode, but cannot be read in subactive mode. when tca overflows, the irrta bit in interrupt request register 1 (irr1) is set to 1. tca is cleared by setting bits tma3 and tma2 of tma to 11. upon reset, tca is initialized to h'00. 9.2.3 timer operation interval timer operation: when bit tma3 in timer mode register a (tma) is cleared to 0, timer a functions as an 8-bit interval timer. upon reset, tca is cleared to h'00 and bit tma3 is cleared to 0, so up-counting and interval timing resume immediately. the clock input to timer a is selected by bits tma2 to tma0 in tma; any of eight internal clock signals output by prescaler s can be selected. after the count value in tca reaches h'ff, the next clock signal input causes timer a to overflow, setting bit irrta to 1 in interrupt request register 1 (irr1). if ienta = 1 in interrupt enable register 1 (ienr1), a cpu interrupt is requested.* at overflow, tca returns to h'00 and starts counting up again. in this mode timer a functions as an interval timer that generates an overflow output at intervals of 256 input clock pulses. note: * for details on interrupts, see 3.3, interrupts. real-time clock time base operation: when bit tma3 in tma is set to 1, timer a functions as a real-time clock time base by counting clock signals output by prescaler w. the overflow period of timer a is set by bits tma1 and tma0 in tma. a choice of four periods is available. in time base operation (tma3 = 1), setting bit tma2 to 1 clears both tca and prescaler w to their initial values of h'00. 156 clock output: setting bit tmow in port mode register 1 (pmr1) to 1 causes a clock signal to be output at pin tmow. eight different clock output signals can be selected by means of bits tma7 to tma5 in tma. the system clock divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. a 32.768 khz signal divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, and subactive mode. 9.2.4 timer a operation states table 9.4 summarizes the timer a operation states. table 9.4 timer a operation states operation mode reset active sleep watch sub- active sub- sleep standby tca interval reset functions functions halted halted halted halted clock time base reset functions functions functions functions functions halted tma reset functions retained retained functions retained retained note: when real-time clock time-base functions are selected as the internal clock of tca in active mode or sleep mode, the internal clock is not synchronous with the system clock, so it is synchronized by a synchronizing circuit. this may result in a maximum error of 1/?(s) in the count cycle. 157 9.3 timer f 9.3.1 overview timer f is a 16-bit timer with an output compare function. compare match signals can be used to reset the counter, request an interrupt, or toggle the output. timer f can also be used for external event counting, and can operate as two independent 8-bit timers, timer fh and timer fl. features: features of timer f are given below. choice of four internal clock sources (?32, ?16, ?4, ?2) or an external clock (can be used as an external event counter). output from pin tmofh is toggled by one compare match signal (the initial value of the toggle output can be set). counter can be reset by the compare match signal. two interrupt sources: counter overflow and compare match. can operate as two independent 8-bit timers (timer fh and timer fl) in 8-bit mode. timer fh ? 8-bit timer (clocked by timer fl overflow signals when timer f operates as a 16-bit timer). ? choice of four internal clocks (?32, ?16, ?4, ?2). ? output from pin tmofh is toggled by one compare match signal (the initial value of the toggle output can be set). ? counter can be reset by the compare match signal. ? two interrupt sources: counter overflow and compare match. timer fl ? 8-bit timer/event counter ? choice of four internal clocks (?32, ?16, ?4, ?2) or event input at pin tmif. ? output from pin tmofl is toggled by one compare match signal (the initial value of the toggle output can be set). ? counter can be reset by the compare match signal. ? two interrupt sources: counter overflow and compare match. 158 block diagram: figure 9.2 shows a block diagram of timer f. pss internal data bus compare circuit ocrfh toggle circuit toggle circuit match legend: tcrf: tcsrf: tcfh: tcfl: ocrfh: ocrfl: timer control register f timer control status register f 8-bit timer counter fh 8-bit timer counter fl output compare register fh output compare register fl irrtfh: irrtfl: pss: timer fh interrupt request flag timer fl interrupt request flag prescaler s irrtfh irrtfl tmif tmofl tmofh tcfl tcrf ocrfl tcfh compare circuit tcsrf figure 9.2 block diagram of timer f 159 pin configuration: table 9.5 shows the timer f pin configuration. table 9.5 pin configuration name abbrev. i/o function timer f event input tmif input event input to tcfl timer fh output tmofh output timer fh toggle output timer fl output tmofl output timer fl toggle output register configuration: table 9.6 shows the register configuration of timer f. table 9.6 timer f registers name abbrev. r/w initial value address timer control register f tcrf w h'00 h'ffb6 timer control/status register f tcsrf r/w h'00 h'ffb7 8-bit timer counter fh tcfh r/w h'00 h'ffb8 8-bit timer counter fl tcfl r/w h'00 h'ffb9 output compare register fh ocrfh r/w h'ff h'ffba output compare register fl ocrfl r/w h'ff h'ffbb 9.3.2 register descriptions 16-bit timer counter (tcf) 8-bit timer counter (tcfh) 8-bit timer counter (tcfl) tcf bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w tcfh tcfl tcf is a 16-bit read/write up-counter consisting of two cascaded 8-bit timer counters, tcfh and tcfl. tcf can be used as a 16-bit counter, with tcfh as the upper 8 bits and tcfl as the lower 8 bits of the counter, or tcfh and tcfl can be used as independent 8-bit counters. 160 tcfh and tcfl can be read and written by the cpu, but in 16-bit mode, data transfer with the cpu takes place via a temporary register (temp). for details see 9.3.3, interface with the cpu. upon reset, tcfh and tcfl are each initialized to h'00. 16-bit mode (tcf): 16-bit mode is selected by clearing bit cksh2 to 0 in timer control register f (tcrf). the tcf input clock is selected by tcrf bits cksl2 to cksl0. timer control status register f (tcsrf) can be set so that counter tcf will be cleared by compare match. when tcf overflows from h'ffff to h'0000, the overflow flag (ovfh) in tcsrf is set to 1. if bit ovieh in tcsrf is set to 1 when an overflow occurs, bit irrtfh in interrupt request register 2 (irr2) will be set to 1; and if bit ientfh in interrupt enable register 2 (ienr2) is set to 1, a cpu interrupt will be requested. 8-bit mode (tcfh, tcfl): when bit cksh2 in timer control register f (tcrf) is set to 1, timer f functions as two separate 8-bit counters, tcfh and tcfl. the tcfh (tcfl) input clock is selected by tcrf bits cksh2 to cksh0 (cksl2 to cksl0). tcfh (tcfl) can be cleared by a compare match signal. this designation is made in bit cclrh (cclrl) in tcsrf. when tcfh (tcfl) overflows from h'ff to h'00, the overflow flag ovfh (ovfl) in tcsrf is set to 1. if bit ovieh (oviel) in tcsrf is set to 1 when an overflow occurs, bit irrtfh (irrthl) in interrupt request register 2 (irr2) will be set to 1; and if bit ientfh (ientfl) in interrupt enable register 2 (ienr2) is set to 1, a cpu interrupt will be requested. 16-bit output compare register (ocrf) 8-bit output compare register (ocrfh) 8-bit output compare register (ocrfl) ocrf bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ocrfh ocrfl ocrf is a 16-bit read/write output compare register consisting of two 8-bit read/write registers ocrfh and ocrfl. it can be used as a 16-bit output compare register, with ocrfh as the 161 upper 8 bits and ocrfl as the lower 8 bits of the register, or ocrfh and ocrfl can be used as independent 8-bit registers. ocrfh and ocrfl can be read and written by the cpu, but in 16-bit mode, data transfer with the cpu takes place via a temporary register (temp). for details see 9.3.3, interface with the cpu. upon reset, ocrfh and ocrfl are each initialized to h'ff. 16-bit mode (ocrf): 16-bit mode is selected by clearing bit cksh2 to 0 in timer control register f (tcrf). the ocrf contents are always compared with the 16-bit timer counter (tcf). when the contents match, the compare match flag (cmfh) in tcsrf is set to 1. also, irrtfh in interrupt request register 2 (irr2) is set to 1. if bit ientfh in interrupt enable register 2 (ienr2) is set to 1, a cpu interrupt is requested. output for pin tmofh can be toggled by compare match. the output level can also be set to high or low by bit tolh of timer control register f (tcrf). 8-bit mode (ocrfh, ocrfl): setting bit cksh2 in tcrf to 1 results in two 8-bit independent registers, ocrfh and ocrfl. the ocrfh contents are always compared with tcfh, and the ocrfl contents are always compared with tcfl. when the contents match, the compare match flag (cmfh or cmfl) in tcsrf is set to 1. also, bit irrtfh (irrtfl) in interrupt request register 2 (irr2) set to 1. if bit ientfh (ientfl) in interrupt enable register 2 (ienr2) is set to 1 at this time, a cpu interrupt is requested. the output at pin tmofh (tmofl) can be toggled by compare match. the output level can also be set to high or low by bit tolh (toll) of the timer control register (tcrf). 162 timer control register f (tcrf) bit 76543210 tolh cksh2 cksh1 cksh0 toll cksl2 cksl1 cksl0 initial value 00000000 read/write wwwwwwww tcrf is an 8-bit write-only register. it is used to switch between 16-bit mode and 8-bit mode, to select among four internal clocks and an external event, and to select the output level at pins tmofh and tmofl. upon reset, tcrf is initialized to h'00. bit 7?oggle output level h (tolh): bit 7 sets the output level at pin tmofh. the setting goes into effect immediately after this bit is written. bit 7: tolh description 0 low level (initial value) 1 high level bits 6 to 4?lock select h (cksh2 to cksh0): bits 6 to 4 select the input to tcfh from four internal clock signals or the overflow of tcfl. bit 6: cksh2 bit 5: cksh1 bit 4: cksh0 description 0 ** 16-bit mode selected. tcfl overflow signals are counted. (initial value) 1 0 0 internal clock: ?32 1 internal clock: ?16 1 0 internal clock: ?4 1 internal clock: ?2 note: * don? care bit 3?oggle output level l (toll): bit 3 sets the output level at pin tmofl. the setting goes into effect immediately after this bit is written. bit 3: toll description 0 low level (initial value) 1 high level 163 bits 2 to 0?lock select l (cksl2 to cksl0): bits 2 to 0 select the input to tcfl from four internal clock signals or external event input. bit 2: cksl2 bit 1: cksl1 bit 0: cksl0 description 0 ** external event (tmif). rising or falling edge is counted (see note). (initial value) 1 0 0 internal clock: ?32 1 internal clock: ?16 1 0 internal clock: ?4 1 internal clock: ?2 *: don? care note: the edge of the external event signal is selected by bit ieg3 in the irq edge select register (iegr). see 3.3.2, interrupt control registers, for details on the irq edge select register. note that switching the tmif pin function by changing bit irq3 in port mode register 1 (pmr1) from 0 to 1 or from 1 to 0 while the tmif pin is at the low level may cause the timer f counter to be incremented. timer control/status register f (tcsrf) bit 76543210 ovfh cmfh ovieh cclrh ovfl cmfl oviel cclrl initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w tcsrf is an 8-bit read/write register. it is used for counter clear selection, overflow and compare match indication, and enabling of interrupts caused by timer overflow. upon reset, tcsrf is initialized to h'00. bit 7?imer overflow flag h (ovfh): bit 7 is a status flag indicating tcfh overflow (h'ff to h'00). this flag is set by hardware and cleared by software. it cannot be set by software. bit 7: ovfh description 0 [clearing conditions] (initial value) after reading ovfh = 1, cleared by writing 0 to ovfh 1 [setting conditions] set when the value of tcfh goes from h'ff to h'00 164 bit 6?ompare match flag h (cmfh): bit 6 is a status flag indicating a compare match between tcfh and ocrfh. this flag is set by hardware and cleared by software. it cannot be set by software. bit 6: cmfh description 0 [clearing conditions] (initial value) after reading cmfh = 1, cleared by writing 0 to cmfh 1 [setting conditions] set when the tcfh value matches ocrfh value bit 5?imer overflow interrupt enable h (ovieh): bit 5 enables or disables tcfh overflow interrupts. bit 5: ovieh description 0 tcfh overflow interrupt disabled (initial value) 1 tcfh overflow interrupt enabled bit 4?ounter clear h (cclrh): in 16-bit mode, bit 4 selects whether or not tcf is cleared when a compare match occurs between tcf and ocrf. in 8-bit mode, bit 4 selects whether or not tcfh is cleared when a compare match occurs between tcfh and ocrfh. bit 4: cclrh description 0 16-bit mode: tcf clearing by compare match disabled (initial value) 8-bit mode: tcfh clearing by compare match disabled 1 16-bit mode: tcf clearing by compare match enabled 8-bit mode: tcfh clearing by compare match enabled bit 3?imer overflow flag l (ovfl): bit 3 is a status flag indicating tcfl overflow (h'ff to h'00). this flag is set by hardware and cleared by software. it cannot be set by software. bit 3: ovfl description 0 [clearing conditions] (initial value) after reading ovfl = 1, cleared by writing 0 to ovfl 1 [setting conditions] set when the value of tcfl goes from h'ff to h'00 165 bit 2?ompare match flag l (cmfl): bit 2 is a status flag indicating a compare match between tcfl and ocrfl. this flag is set by hardware and cleared by software. it cannot be set by software. bit 2: cmfl description 0 [clearing conditions] (initial value) after reading cmfl = 1, cleared by writing 0 to cmfl 1 [setting conditions] set when the tcfl value matches the ocrfl value bit 1?imer overflow interrupt enable l (oviel): bit 1 enables or disables tcfl overflow interrupts. bit 1: oviel description 0 tcfl overflow interrupt disabled (initial value) 1 tcfl overflow interrupt enabled bit 0?ounter clear l (cclrl): bit 0 selects whether or not tcfl is cleared when a compare match occurs between tcfl and ocrfl. bit 0: cclrl description 0 tcfl clearing by compare match disabled (initial value) 1 tcfl clearing by compare match enabled 166 9.3.3 interface with the cpu tcf and ocrf are 16-bit read/write registers, whereas the data bus between the cpu and on-chip peripheral modules has an 8-bit width. for this reason, when the cpu accesses tcf or ocrf, it makes use of an 8-bit temporary register (temp). in 16-bit mode, when reading or writing tcf or writing ocrf, always use two consecutive byte size mov instructions, and always access the upper byte first. data will not be transferred properly if only the upper byte or only the lower byte is accessed. in 8-bit mode there is no such restriction on the order of access. write access: when the upper byte is written, the upper-byte data is loaded into the temp register. next when the lower byte is written, the data in temp goes to the upper byte of the register, and the lower-byte data goes directly to the lower byte of the register. figure 9.3 shows a tcf write operation when h'aa55 is written to tcf. read access: when the upper byte of tcf is read, the upper-byte data is sent directly to the cpu, and the lower byte is loaded into temp. next when the lower byte is read, the lower byte in temp is sent to the cpu. when the upper byte of ocrf is read, the upper-byte data is sent directly to the cpu. next when the lower byte is read, the lower-byte data is sent directly to the cpu. figure 9.4 shows a tcf read operation when h'aaff is read from tcf. 167 bus interface cpu [h'aa] temp [h'aa] tcfh [ ] tcfl [ ] internal data bus when writing the upper byte cpu [h'55] temp [h'aa] tcfh [h'aa] tcfl [h'55] internal data bus when writing the lower byte bus interface figure 9.3 tcf write operation (cpu ? tcf) 168 bus interface bus interface cpu [h'aa] temp (h'ff) tcfh [h'aa] tcfl [h'ff] internal data bus when reading the upper byte cpu [h'ff] temp [h'ff] tcfh [ab] tcfl [00] internal data bus when reading the lower byte ** note: * becomes h'ab00 if counter is incremented once. figure 9.4 tcf read operation (tcf ? cpu) 169 9.3.4 timer operation timer f is a 16-bit timer/counter that increments with each input clock. when the value set in output compare register f matches the count in timer f, the timer can be cleared, an interrupt can be requested, and the port output can be toggled. timer f can also be used as two independent 8-bit timers. timer f operation: timer f can operate in either 16-bit timer mode or 8-bit timer mode. these modes are described below. 16-bit timer mode timer f operates in 16-bit timer mode when the cksh2 bit in timer control register f (tcrf) is cleared to 0. a reset initializes timer counter f (tcf) to h'0000, output compare register f (ocrf) to h'ffff, and timer control register f (tcrf) and timer control status register f (tcsrf) to h'00. timer f begins counting external event input signals (tmif). the edge of the external event signal is selected by the ieg3 bit in the irq edge select register (iegr). the operational clock of timer f can be selected by setting bits cskl2 through cksl0 in tcrf, from four internal clocks output from prescaler s as well as from an external clock. tcf is continuously compared with the contents of ocrf. when these two values match, the cmfh bit in tcsrf is set to 1. at this time if ientfh of ienr2 is 1, a cpu interrupt is requested and the output at pin tmofh is toggled. if the cclrh bit in tcsrf is 1, tcf is cleared. the output at pin tmofh can also be set by the tolh bit in tcrf. if timer f overflows (from h'ffff to h'0000), the ovfh bit in tcsrf is set to 1. at this time, if the ovieh bit in tcsrf and the ientfh bit in ienr2 are both 1, cpu interrupt is requested. 8-bit timer mode when the cksh2 bit in tcrf is set to 1, timer f operates as two independent 8-bit timers, tcfh and tcfl. the input clock of tcfh/tcfl is selected by bits cksh2 to cksh0/cksl2 to cksl0 in tcrf. when tcfh/tcfl and the contents of ocrfh/ocrfl match, the cmfh/cmfl bit in tcsrf is set to 1. if the ientfh/ientfl bit in ienr2 is 1, a cpu interrupt is requested and the output at pin tmofh/tmofl is toggled. if the cclrh/cclrl bit in tcrf is 1, tcfh/tcfl is cleared. the output at pin tmofh/tmofl can also be set by the tolh/toll bit in tcrf. when tcfh/tcfl overflows from h'ff to h'00, the ovfh/ovfl bit in tcsrf is set to 1. at this time, if the ovieh/oviel bit in tcsrf and the ientfh/ientfl bit in ienr2 are both 1, a cpu interrupt is requested. 170 tcf count timing: tcf is incremented by each pulse of the input clock (internal clock or external event). internal clock the settings of bits cksh2 to cksh0 or bits cksl2 to cksl0 in tcrf select one of four internal clock signals (?32, ?16, ?4, or ?2) divided from the system clock (?. external event external event input is selected by clearing bit cksl2 to 0 in tcrf. either rising or falling edges of the clock input can be counted. the edge is selected by bit ieg3 in iegr. an external clock pulse width of at least two system clock cycles (? is necessary; otherwise the counter will not operate properly. tmofh and tmofl output timing: the outputs at pins tmofh and tmofl are the values set in bits tolh and toll in tcrf. when a compare match occurs, the output value is inverted. figure 9.5 shows the output timing. tmif (when ieg3 = 1) count input clock tcf ocrf compare match signal tmofh, tmofl n n + 1 n n + 1 nn figure 9.5 tmofh, tmofl output timing tcf clear timing: tcf can be cleared at compare match with ocrf. timer overflow flag (ovf) set timing: ovf is set to 1 when tcf overflows (goes from h'ffff to h'0000). 171 compare match flag set timing: the compare match flags (cmfh or cmfl) are set to 1 when a compare match occurs between tcf and ocrf. a compare match signal is generated in the final state in which the values match (when tcf changes from the matching count value to the next value). when tcf and ocrf match, a compare match signal is not generated until the next counter clock pulse. timer f operation states: table 9.7 summarizes the timer f operation states. table 9.7 timer f operation states operation mode reset active sleep watch sub- active sub- sleep standby tcf reset functions functions halted halted halted halted ocrf reset functions retained retained retained retained retained tcrf reset functions retained retained retained retained retained tcsrf reset functions retained retained retained retained retained 9.3.5 application notes the following conflicts can arise in timer f operation. 16-bit timer mode: the output at pin tmofh toggles when all 16 bits match and a compare match signal is generated. if the compare match signal occurs at the same time as new data is written in tcrf by a mov instruction, however, the new value written in bit tolh will be output at pin tmofh. the tmofl output in 16-bit mode is indeterminate, so this output should not be used. use the pin as a general input or output port. if an ocrfl write occurs at the same time as a compare match signal, the compare match signal is inhibited. if a compare match occurs between the written data and the counter value, however, a compare match signal will be generated at that point. the compare match signal is output in synchronization with the tcfl clock, so if this clock is stopped no compare match signal will be generated, even if a compare match occurs. compare match flag cmfh is set when all 16 bits match and a compare match signal is generated; bit cmfl is set when the setting conditions are met for the lower 8 bits. the overflow flag (ovfh) is set when tcf overflows; bit ovfl is set if the setting conditions are met when the lower 8 bits overflow. if a write to tcfl occurs at the same time as an overflow signal, the overflow signal is not output. 172 8-bit timer mode tcfh and ocrfh the output at pin tmofh toggles when there is a compare match. if the compare match signal occurs at the same time as new data is written in tcrf by a mov instruction, however, the new value written in bit tolh will be output at pin tmofh. if an ocrfh write occurs at the same time as a compare match signal, the compare match signal is inhibited. if a compare match occurs between the written data and the counter value, however, a compare match signal will be generated at that point. the compare match signal is output in synchronization with the tcfh clock. if a tcfh write occurs at the same time as an overflow signal, the overflow signal is not output. tcfl and ocrfl the output at pin tmofl toggles when there is a compare match. if the compare match signal occurs at the same time as new data is written in tcrf by a mov instruction, however, the new value written in bit toll will be output at pin tmofl. if an ocrfl write occurs at the same time as a compare match signal, the compare match signal is inhibited. if a compare match occurs between the written data and the counter value, however, a compare match signal will be generated at that point. the compare match signal is output in synchronization with the tcfl clock, so if this clock is stopped no compare match signal will be generated, even if a compare match occurs. if a tcfl write occurs at the same time as an overflow signal, the overflow signal is not output. 173 9.4 timer g 9.4.1 overview timer g is an 8-bit timer, with input capture/interval functions for separately capturing the rising edge and falling edge of pulses input at the input capture pin (input capture input signal). timer g has a built-in noise canceller circuit that can eliminate high-frequency noise from the input capture signal, enabling accurate measurement of its duty cycle. when timer g is not used for input capture, it functions as an 8-bit interval timer. features: features of timer g are given below. choice of four internal clock sources (?64, ?32, ?2, w /2) input capture function separate input capture functions are provided for the rising and falling edges. counter overflow detection can detect whether overflow occurred when the input capture signal was high or low. choice of counter clear it is possible to select whether or not the counter is cleared at the rising edge, falling edge, or both edges of the input capture input signal. two interrupt sources there is one input capture interrupt source and one overflow interrupt source. for input capture, the rising or falling edge can be selected. built-in noise-canceller circuit the noise canceller circuit can eliminate high-frequency noise in the input capture signal. operates in subactive and subsleep modes when w /2 is selected as the internal clock source, timer g can operate in the subactive and subsleep modes. 174 block diagram: figure 9.6 shows a block diagram of timer g. legend: pss tmg icrgf tcg icrgr irrtg internal data bus level sense circuit noise canceller circuit edge sense circuit ? /2 tmig ncs w tmg: tcg: icrgf: icrgr: irrtg: ncs: pss: timer mode register g timer counter g input capture register gf input capture register gr timer g interrupt request flag noise canceller select prescaler s figure 9.6 block diagram of timer g pin configuration: table 9.8 shows the timer g pin configuration. table 9.8 pin configuration name abbrev. i/o function input capture input tmig input input capture 175 register configuration: table 9.9 shows the register configuration of timer g. table 9.9 timer g registers name abbrev. r/w initial value address timer mode register g tmg r/w h'00 h'ffbc timer counter g tcg h'00 input capture register gf icrgf r h'00 h'ffbd input capture register gr icrgr r h'00 h'ffbe 9.4.2 register descriptions timer counter g (tcg) bit 76543210 tcg7 tcg6 tcg5 tcg4 tcg3 tcg2 tcg1 tcg0 initial value 00000000 read/write timer counter g (tcg) is an 8-bit up-counter which is incremented by an input clock. the input clock signal is selected by bits cks1 and cks0 in timer mode register g (tmg). to use tcg as an input capture timer, set bit tmig to 1 in pmr1; to use tcg as an interval timer, clear bit tmig to 0.* when tcg is used as an input capture timer, the tcg value can be cleared at the rising edge, falling edge, or both edges of the input capture signal, depending on settings in tmg. when tcg overflows (goes from h'ff to h'00), if the timer overflow interrupt enable bit (ovie) is set to 1 in tmg, bit irrtg in interrupt request register 2 (irr2) is set to 1. if in addition bit ientg in interrupt enable register 2 (ienr2) is set to 1, a cpu interrupt is requested. details on interrupts are given in 3.3, interrupts. tcg cannot be read or written by the cpu. upon reset, tcg is initialized to h'00. note: * an input capture signal may be generated when tmig is rewritten. 176 input capture register gf (icrgf) bit 76543210 icrgf7 icrgf6 icrgf5 icrgf4 icrgf3 icrgf2 icrgf1 icrgf0 initial value 00000000 read/write rrrrrrrr icrgf is an 8-bit read-only register. when the falling edge of the input capture signal is detected, the tcg value at that time is transferred to icrgf. if the input capture interrupt select bit (iiegs) is set to 1 in tmg, bit irrtg in interrupt request register 2 (irr2) is set to 1. if in addition bit ientg in interrupt enable register 2 (ienr2) is set to 1, a cpu interrupt is requested. details on interrupts are given in 3.3, interrupts. to ensure proper input capture when the noise canceller is not used, the pulse width of the input capture signal should be at least 2?or 2 sub . upon reset, icrgf is initialized to h'00. input capture register gr (icrgr) bit 76543210 icrgr7 icrgr6 icrgr5 icrgr4 icrgr3 icrgr2 icrgr1 icrgr0 initial value 00000000 read/write rrrrrrrr icrgr is an 8-bit read-only register. when the rising edge of the input capture signal is detected, the tcg value at that time is sent to icrgr. if the iiegs bit is cleared to 0 in tmg, bit irrtg in interrupt request register 2 (irr2) is set to 1. if in addition bit ientg in interrupt enable register 2 (ienr2) is set to 1, a cpu interrupt is requested. details on interrupts are given in 3.3, interrupts. to ensure proper input capture when the noise canceller is not used, the pulse width of the input capture signal should be at least 2?or 2 sub . upon reset, icrgr is initialized to h'00. 177 timer mode register g (tmg) bit 76543210 ovfh ovfl ovie iiegs cclr1 cclr0 cks1 cks0 initial value 00000000 read/write r/w * r/w * r/w r/w r/w r/w r/w r/w note: * only 0 can be written, to clear flag. tmg is an 8-bit read/write register. it controls the choice of four internal clocks, counter clear selection, and edge selection for input capture interrupt requests. it also indicates overflow status and enables or disables overflow interrupt requests. upon reset, tmg is initialized to h'00. bit 7?imer overflow flag h (ovfh): bit 7 is a status flag indicating that tcg overflowed (from h'ff to h'00) when the input capture signal was high. this flag is set by hardware and cleared by software. it cannot be set by software. bit 7: ovfh description 0 [clearing conditions] (initial value) after reading ovfh = 1, cleared by writing 0 to ovfh 1 [setting conditions] set when the value of tcg overflows from h'ff to h'00 bit 6?imer overflow flag l (ovfl): bit 6 is a status flag indicating that tcg overflowed (from h'ff to h'00) when the input capture signal was low, or in interval timer operation. this flag is set by hardware and cleared by software. it cannot be set by software. bit 6: ovfl description 0 [clearing conditions] (initial value) after reading ovfl = 1, cleared by writing 0 to ovfl 1 [setting conditions] set when the value of tcg overflows from h'ff to h'00 bit 5?imer overflow interrupt enable (ovie): bit 5 enables or disables tcg overflow interrupts. bit 5: ovie description 0 tcg overflow interrupt disabled (initial value) 1 tcg overflow interrupt enabled 178 bit 4?nput capture interrupt edge select (iiegs): bit 4 selects the input signal edge at which input capture interrupts are requested. bit 4: iiegs description 0 interrupts are requested at the rising edge of the input capture signal (initial value) 1 interrupts are requested at the falling edge of the input capture signal bits 3, 2?ounter clear 1, 0 (cclr1, cclr0): bits 3 and 2 designate whether tcg is cleared at the rising, falling, or both edges of the input capture signal, or is not cleared. bit 3: cclr1 bit 2: cclr0 description 0 0 tcg is not cleared (initial value) 1 tcg is cleared at the falling edge of the input capture signal 1 0 tcg is cleared at the rising edge of the input capture signal 1 tcg is cleared at both edges of the input capture signal bits 1, 0?lock select (cks1, cks0): bits 1 and 0 select the clock input to tcg from four internal clock signals. bit 1: cks1 bit 0: cks0 description 0 0 internal clock: ?64 (initial value) 1 internal clock: ?32 1 0 internal clock: ?2 1 internal clock: w /2 179 9.4.3 noise canceller circuit the noise canceller circuit built into the h8/3637 series is a digital low-pass filter that rejects high-frequency pulse noise in the input at the input capture pin. the noise canceller circuit is enabled by the noise canceller select (ncs)* bit in port mode register 2 (pmr2). figure 9.7 shows a block diagram of the noise canceller circuit. input capture signal sampling clock match detection circuit noise canceller output t: selected by bits cks1, cks0. sampling clock c latch d q c latch d q c latch d q c latch d q c latch d q d t d figure 9.7 block diagram of noise canceller circuit the noise canceller consists of five latch circuits connected in series, and a match detection circuit. when the noise canceller function is disabled (ncs = 0), the system clock is selected as the sampling clock. when the noise canceller is enabled (ncs = 1), the internal clock selected by bits cks1 and cks0 in tmg becomes the sampling clock. the input signal is sampled at the rising edge of this clock pulse. data is considered correct when the outputs of all five latch circuits match. if they do not match, the previous value is retained. upon reset, the noise canceller output is initialized after the falling edge of the input capture signal has been sampled five times. accordingly, after the noise canceller function is enabled, pulses that have a pulse width five times greater than the sampling clock will be recognized as input capture signals. if the noise canceller circuit is not used, the input capture signal pulse width must be at least 2?or 2 sub in order to ensure proper input capture operation. note: rewriting the ncs bit may cause an internal input capture signal to be generated. 180 figure 9.8 shows a typical timing diagram for the noise canceller circuit. in this example, a high- level input at the input capture pin is rejected as noise because its pulse width is less than five sampling clock ?cycles. input capture input signal sampling clock noise canceller output rejected as noise figure 9.8 noise canceller circuit timing (example) 9.4.4 timer operation timer g functions: timer g is an 8-bit up-counter that functions as an input capture timer or an interval timer. these two functions are described below. input capture timer operation timer g functions as an input capture timer when bit tmig of port mode register 1 (pmr1) is set to 1.* at reset, timer mode register g (tmg), timer counter g (tcg), input capture register gf (icrgf), and input capture register gr (icrgr) are all initialized to h'00. immediately after reset, tcg begins counting an internal clock with a frequency of ?divided by 64 (?64). the clock to be input can be selected by using bits cks1 and cks0 in tmg from four internal clock sources. at the rising edge/falling edge of the input capture signal input to pin tmig, the value of tcg is copied into icrgr/icrgf. if the input edge is the same as the edge selected by the iiegs bit of tmg, then bit irrtg is set to 1 in irr2. if bit ientg is also set to 1 in ienr2, a cpu interrupt is requested. for details on interrupts, see 3.3, interrupts. tcg can be cleared to 0 at the rising edge, falling edge, or both edges of the input capture signal as determined with bits cclr1 and cclr0 of tmg. if tcg overflows while the input capture signal is high, bit ovfh of tmg is set. if tcg overflows while the input capture signal is low, bit ovfl of tmg is set. when either of these bits is set, if bit ovie of tmg is currently set to 1, then bit irrtg is set to 1 in irr2. if bit ientg is also set to 1 in ienr2, then timer g requests a cpu interrupt. for further details see 3.3, interrupts. 181 timer g has a noise canceller circuit that rejects high-frequency pulse noise in the input to pin tmig. see 9.4.3, noise canceller circuit, for details. note: * rewriting the tmig bit may cause an internal input capture signal to be generated. interval timer operation timer g functions as an interval timer when bit tmig is cleared to 0 in pmr1. following a reset, tcg starts counting cycles of the ?64 internal clock. this is one of four internal clock sources that can be selected by bits cks1 and cks0 of tmg. tcg counts up according to the selected clock source. when it overflows from h'ff to h'00, bit ovfl of tmg is set to 1. if bit ovie of tmg is currently set to 1, then bit irrtg is set to 1 in irr2. if bit ientg is also set to 1 in ienr2, then timer g requests a cpu interrupt. for further details see 3.3, interrupts. count timing: tcg is incremented by input pulses from an internal clock. tmg bits cks1 and cks0 select one of four internal clocks (?64, ?32, ?2, w /2) derived by dividing the system clock (? and the watch clock ( w ). timing of internal input capture signals: timing with noise canceller function disabled separate internal input capture signals are generated from the rising and falling edges of the external input signal. figure 9.9 shows the timing of these signals. external input capture signal internal input capture signal f internal input capture signal r figure 9.9 input capture signal timing (noise canceller function disabled) 182 timing with noise canceller function enabled when input capture noise cancelling is enabled, the external input capture signal is routed via the noise canceller circuit, so the internal signals are delayed from the input edge by five sampling clock cycles. figure 9.10 shows the timing. external input capture signal sampling clock noise canceller circuit output internal input capture signal r figure 9.10 input capture signal timing (noise canceller function enabled) timing of input capture: figure 9.11 shows the input capture timing in relation to the internal input capture signal. internal input capture signal tcg input capture register n ? n n +1 h'xx n figure 9.11 input capture timing 183 tcg clear timing: tcg can be cleared at the rising edge, falling edge, or both edges of the external input capture signal. figure 9.12 shows the timing for clearing at both edges. external input capture signal internal input capture signal f internal input capture signal r tcg n h'00 n h'00 figure 9.12 tcg clear timing timer g operation states: table 9.10 summarizes the timer g operation states. table 9.10 timer g operation states operation mode reset active sleep watch sub- active sub- sleep standby tcg input capture reset functions * functions * halted functions/ halted * functions/ halted * halted interval reset functions * functions * retained functions/ halted * functions/ halted * halted icrgf reset functions * functions * retained functions/ halted * functions/ halted * retained icrgr reset functions * functions * retained functions/ halted * functions/ halted * retained tmg reset functions retained retained functions retained retained note: * in active mode and sleep mode, if w /2 is selected as the tcg internal clock, since the system clock and internal clock are not synchronized with each other, a synchronization circuit is used. this may result in a count cycle error of up to 1/?(s). in subactive mode and subsleep mode, if w /2 is selected as the tcg internal clock, regardless of the subclock ?sub ( w /2, w /4, w /8) tcg and the noise canceller circuit run on an internal clock of w /2. if any other internal clock is chosen, tcg and the noise canceller circuit will not run, and the input capture function will not operate. 184 9.4.5 application notes input clock switching and tcg operation: depending on when the input clock is switched, there will be cases in which tcg is incremented in the process. table 9.11 shows the relation between internal clock switchover timing (selected in bits cks1 and cks0) and tcg operation. if an internal clock (derived from the system clock ?or subclock sub ) is used, an increment pulse is generated when a falling edge of the internal clock is detected. for this reason, in a case like no. 3 in table 9.11, where the clock is switched at a time such that the clock signal goes from high level before switching to low level after switching, the switchover is seen as a falling edge to generate the count clock, causing tcg to be incremented. table 9.11 internal clock switching and tcg operation no. clock levels before and after modifying bits cks1 and cks0 tcg operation 1 goes from low level to low level n +1 clock before switching clock after switching count clock tcg cks bits modified n 2 goes from low level to high level n +1 n +2 clock before switching clock after switching count clock tcg cks bits modified n 185 table 9.11 internal clock switching and tcg operation (cont) no. clock levels before and after modifying bits cks1 and cks0 tcg operation 3 goes from high level to low level n +1 n n +2 * clock before switching clock after switching count clock tcg cks bits modified 4 goes from high level to high level n +1 n +2 n clock before switching clock after switching count clock cks bits modified tcg note: * the switchover is seen as a falling edge of the clock pulse, and tcg is incremented. 186 note on rewriting port mode registers: when a port mode register setting is modified to enable or disable the input capture function or input capture noise canceling function, note the following points. switching the function of the input capture pin when the function of the input capture pin is switched by modifying port mode register 1 (pmr1) bit 3 (the tmig bit), an input capture edge may be recognized even though no valid signal edge has been input. this occurs under the conditions listed in table 9.12. table 9.12 false input capture edges generating by switching of input capture pin function input capture edge conditions rising edge recognized tmig pin level is high, and tmig bit is changed from 0 to 1 tmig pin level is high and ncs bit is changed from 0 to 1, then tmig bit is changed from 0 to 1 before noise canceller circuit completes five samples falling edge recognized tmig pin level is high, and tmig bit is changed from 1 to 0 tmig pin level is low and ncs bit is changed from 0 to 1, then tmig bit is changed from 0 to 1 before noise canceller circuit completes five samples tmig pin level is high and ncs bit is changed from 0 to 1, then tmig bit is changed from 1 to 0 before noise canceller circuit completes five samples note: when pin p1 3 is not used for input capture, the input capture signal input to timer g is low. switching the input capture noise canceling function when modifying port mode register 2 (pmr2) bit 4 (the ncs bit) to enable or disable the input capture noise canceling function, first clear the tmig bit to 0. otherwise an input capture edge may be recognized even though no valid signal edge has been input. this occurs under the conditions listed in table 9.13. table 9.13 false input capture edges generating by switching of noise canceling function input capture edge conditions rising edge recognized tmig bit is set to 1 and tmig pin level changes from low to high, then ncs bit is changed from 1 to 0 before noise canceller circuit completes five samples falling edge recognized tmig bit is set to 1 and tmig pin level changes from high to low, then ncs bit is changed from 1 to 0 before noise canceller circuit completes five samples 187 if switching of the pin function generates a false input capture edge matching the edge selected by the input capture interrupt edge select bit (iiegs), the interrupt request flag will be set to 1, making it necessary to clear this flag to 0 before using the interrupt function. figure 9.13 shows the procedure for modifying port mode register settings and clearing the interrupt request flag. the first step is to mask interrupts before modifying the port mode register. after modifying the port mode register setting, wait long enough for an input capture edge to be recognized (at least two system clocks when noise canceling is disabled; at least five sampling clocks when noise canceling is enabled), then clear the interrupt request flag to 0 (assuming it has been set to 1). an alternative procedure is to avoid having the interrupt request flag set when the pin function is switched, either by controlling the level of the input capture pin so that it does not satisfy the conditions in tables 9.12 and 9.13, or by setting the iiegs bit of tmg to select the edge opposite to the falsely generated edge. set i bit to 1 in ccr clear i bit to 0 in ccr modify port mode register wait for tmig to be recognized clear interrupt request flag to 0 disable interrupts (or disable by clearing interrupt enable bit in interrupt enable register 2) modify port mode register setting, wait for input capture edge to be recognized (at least two system clocks when noise canceling is disabled; at least five sampling clocks when noise canceling is enabled), then clear interrupt request flag to 0 enable interrupts figure 9.13 procedure for modifying port mode register and clearing interrupt request flag 188 9.4.6 sample timer g application the absolute values of the high and low widths of the input capture signal can be measured by using timer g. the cclr1 and cclr0 bits of tmg should be set to 1. figure 9.14 shows an example of this operation. input capture signal h'ff input capture register gf input capture register gr h'00 counter cleared tcg figure 9.14 sample timer g application 189 section 10 serial communication interface 10.1 overview the h8/3627 series is provided with a two-channel serial communication interface (sci), sci1 and sci3. table 10.1 summarizes the functions and features of the two sci channels. table 10.1 serial communication interface functions channel functions features sci1 synchronous serial transfer choice of 8-bit or 16-bit data length continuous clock output choice of 8 internal clocks (?1024 to ?2) or external clock open drain output possible interrupt requested at completion of transfer sci3 synchronous serial transfer 8-bit data transfer send, receive, or simultaneous send/receive asynchronous serial transfer multiprocessor communication function choice of 7-bit or 8-bit data length choice of 1-bit or 2-bit stop bit length odd or even parity built-in baud rate generator receive error detection break detection interrupt requested at completion of transfer or error 10.2 sci1 10.2.1 overview serial communication interface 1 (sci1) performs synchronous serial transfer of 8-bit or 16-bit data. features: features of sci1 are given below. choice of 8-bit or 16-bit data length choice of eight internal clock sources (?1024, ?256, ?64, ?32, ?16, ?8, ?4, ?2) or an external clock interrupt requested at completion of transfer 190 block diagram: figure 10.1 shows a block diagram of sci1. sck 1 si 1 so 1 scr1 scsr1 sdru sdrl pss transfer bit counter transmit/receive control circuit internal data bus legend: scr1: scsr1: sdru: sdrl: irrs1: pss: serial control register 1 serial control/status register 1 serial data register u serial data register l sci1 interrupt request flag prescaler s irrs1 figure 10.1 sci1 block diagram pin configuration: table 10.2 shows the sci1 pin configuration. table 10.2 pin configuration name abbrev. i/o function sci1 clock pin sck 1 i/o sci1 clock input or output sci1 data input pin si 1 input sci1 receive data input sci1 data output pin so 1 output sci1 transmit data output 191 register configuration: table 10.3 shows the sci1 register configuration. table 10.3 sci1 registers name abbrev. r/w initial value address serial control register 1 scr1 r/w h'00 h'ffa0 serial control status register 1 scsr1 r/w h'9c h'ffa1 serial data register u sdru r/w undefined h'ffa2 serial data register l sdrl r/w undefined h'ffa3 10.2.2 register descriptions serial control register 1 (scr1) bit 76543210 snc1 snc0 cks3 cks2 cks1 cks0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w scr1 is an 8-bit read/write register for selecting the operation mode, the transfer clock source, and the prescaler division ratio. upon reset, scr1 is initialized to h'00. writing to this register stops a transfer in progress. bits 7 and 6?peration mode select 1, 0 (snc1, snc0): bits 7 and 6 select the operation mode. bit 7: snc1 bit 6: snc0 description 0 0 8-bit synchronous transfer mode (initial value) 1 16-bit synchronous transfer mode 1 0 continuous clock output mode * 1 1 reserved * 2 notes: 1. pins si 1 and so 1 should be used as general input or output ports. 2. don? set bits snc1 and snc0 to 11. bits 5 and 4?eserved bits: bits 5 and 4 are reserved: they should always be cleared to 0. 192 bit 3?lock source select 3 (cks3): bit 3 selects the clock source and sets pin sck 1 as an input or output pin. bit 3: cks3 description 0 clock source is prescaler s, and pin sck 1 is output pin (initial value) 1 clock source is external clock, and pin sck 1 is input pin bits 2 to 0?lock select 2 to 0 (cks2 to cks 0): when cks3 = 0, bits 2 to 0 select the prescaler division ratio and the serial clock cycle. serial clock cycle bit 2: cks2 bit 1: cks1 bit 0: cks0 prescaler division ?= 5 mhz ?= 2.5 mhz 0 0 0 ?1024 (initial value) 204.8 m s 409.6 m s 1 ?256 51.2 m s 102.4 m s 1 0 ?64 12.8 m s 25.6 m s 1 ?32 6.4 m s 12.8 m s 1 0 0 ?16 3.2 m s 6.4 m s 1 ?8 1.6 m s 3.2 m s 1 0 ?4 0.8 m s 1.6 m s 1 ?2 0.8 m s serial control/status register 1 (scsr1) bit 76543210 sol orer stf initial value 10011100 read/write r/w r/(w) * rr/w note: * only a write of 0 for flag clearing is possible. scsr1 is an 8-bit read/write register indicating operation status and error status. upon reset, scsr1 is initialized to h'9c. bit 7?eserved bit: bit 7 is reserved; it is always read as 1, and cannot be modified. 193 bit 6?xtended data bit (sol): bit 6 sets the so 1 output level. when read, sol returns the output level at the so 1 pin. after completion of a transmission, so 1 continues to output the value of the last bit of transmitted data. the so 1 output can be changed by writing to sol before or after a transmission. the sol bit setting remains valid only until the start of the next transmission. to control the level of the so 1 pin after transmission ends, it is necessary to write to the sol bit at the end of each transmission. do not write to this register while transmission is in progress, because that may cause a malfunction. bit 6: sol description 0 read so 1 pin output level is low (initial value) write so 1 pin output level changes to low 1 read so 1 pin output level is high write so 1 pin output level changes to high bit 5?verrun error flag (orer): when an external clock is used, bit 5 indicates the occurrence of an overrun error. if a clock pulse is input after transfer completion, this bit is set to 1 indicating an overrun. if noise occurs during a transfer, causing an extraneous pulse to be superimposed on the normal serial clock, incorrect data may be transferred. bit 5: orer description 0 [clearing conditions] (initial value) after reading orer = 1, cleared by writing 0 to orer 1 [setting conditions] set if a clock pulse is input after transfer is complete, when an external clock is used bits 4 to 2?eserved bits: bits 4 to 2 are reserved; they are always read as 1, and cannot be modified. bit 1?eserved bit: bit 1 is reserved; and cannot be modified. this bit will be read as 0 after a reset, but its value is undefined at other times. bit 0?tart flag (stf): bit 0 controls the start of a transfer. setting this bit to 1 causes sci1 to start transferring data. during the transfer or while waiting for start bit, this bit remains set to 1. it is cleared to 0 upon completion of the transfer. it can therefore be used as a busy flag. 194 bit 0: stf description 0 read indicates that transfer is stopped (initial value) write invalid 1 read indicates transfer in progress write starts a transfer operation serial data register u (sdru) bit 76543210 sdru7 sdru6 sdru5 sdru4 sdru3 sdru2 sdru1 sdru0 initial value undefined undefined undefined undefined undefined undefined undefined undefined read/write r/w r/w r/w r/w r/w r/w r/w r/w sdru is an 8-bit read/write register. it is used as the data register for the upper 8 bits in 16-bit transfer (sdrl is used for the lower 8 bits). data written to sdru is output to sdrl starting from the least significant bit (lsb). this data is then replaced by lsb-first data input at pin si 1 , which is shifted in the direction from the most significant bit (msb) toward the lsb. sdru must be written or read only after data transmission or reception is complete. if this register is written or read while a data transfer is in progress, the data contents are not guaranteed. the sdru value upon reset is not fixed. serial data register l (sdrl) bit 76543210 sdrl7 sdrl6 sdrl5 sdrl4 sdrl3 sdrl2 sdrl1 sdrl0 initial value undefined undefined undefined undefined undefined undefined undefined undefined read/write r/w r/w r/w r/w r/w r/w r/w r/w sdrl is an 8-bit read/write register. it is used as the data register in 8-bit transfer, and as the data register for the lower 8 bits in 16-bit transfer (sdru is used for the upper 8 bits). in 8-bit transfer, data written to sdrl is output from pin so 1 starting from the least significant bit (lsb). this data is than replaced by lsb-first data input at pin si 1 , which is shifted in the direction from the most significant bit (msb) toward the lsb. in 16-bit transfer, operation is the same as for 8-bit transfer, except that input data is fed in via sdru. 195 sdrl must be written or read only after data transmission or reception is complete. if this register is read or written while a data transfer is in progress, the data contents are not guaranteed. the sdrl value upon reset is not fixed. 10.2.3 operation data can be sent and received in an 8-bit or 16-bit format, synchronized to an internal or external clock. overrun errors can be detected when an external clock is used. (1) clock the serial clock can be selected from a choice of eight internal clocks and an external clock. when an internal clock source is selected, pin sck 1 becomes the clock output pin. when continuous clock output mode is selected (scr1 bits snc1 and snc0 are set to 10), the clock signal (?1024 to ?2) selected in bits cks2 to cks0 is output continuously from pin sck 1 . when an external clock is used, pin sck 1 is the clock input pin. (2) data transfer format figure 10.2 shows the data transfer format. data is sent and received starting from the least significant bit, in lsb-first format. transmit data is output from one falling edge of the serial clock until the next falling edge. receive data is latched at the rising edge of the serial clock. sck so /si 1 11 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 figure 10.2 transfer format (3) data transfer operations transmitting: a transmit operation is carried out as follows. 1. set bits so1 and sck1 in pmr2 to 1, selecting the so 1 and sck 1 pin functions. if necessary, set bit pof1 in pmr2 for nmos open drain output at pin so 1 . 2. clear bit snc1 in scr1 to 0, and set bit snc0 to 1 or 0, designating 8- or 16-bit synchronous transfer mode. select the serial clock in bits cks3 to cks0. writing data to scr1 initializes the internal state of sci1. 3. write transmit data in sdrl and sdru, as follows. 8-bit transfer mode: sdrl 16-bit transfer mode: upper byte in sdru, lower byte in sdrl 4. set the scsr1 start flag (stf) to 1. sci1 starts operating and outputs transmit data at pin so 1 . 196 5. after data transmission is complete, bit irrs1 in interrupt request register 1 (irr1) is set to 1. when an internal clock is used, a serial clock is output from pin sck 1 in synchronization with the transmit data. after data transmission is complete, the serial clock is not output until the next time the start flag is set to 1. during this time, pin so 1 continues to output the value of the last bit transmitted. when an external clock is used, data is transmitted in synchronization with the serial clock input at pin sck 1 . after data transmission is complete, an overrun occurs if the serial clock continues to be input; no data is transmitted and the scsr1 overrun error flag (bit orer) is set to 1. while transmission is stopped, the output value of pin so 1 can be changed by rewriting bit sol in scsr1. receiving: a receive operation is carried out as follows. 1. set bits si1 and sck1 in pmr2 to 1, selecting the si 1 and sck 1 pin functions. 2. clear bit snc1 in scr1 to 0, and set bit snc0 to 1 or 0, designating 8- or 16-bit synchronous transfer mode. select the serial clock in bits cks3 to cks0. writing data to scr1 initializes the internal state of sci1. 3. set the scsr1 start flag (stf) to 1. sci1 starts operating and receives data at pin si 1 . 4. after data reception is complete, bit irrs1 in interrupt request register 1 (irr1) is set to 1. 5. read the received data from sdrl and sdru, as follows. 8-bit transfer mode: sdrl 16-bit transfer mode: upper byte in sdru, lower byte in sdrl 6. after data reception is complete, an overrun occurs if the serial clock continues to be input; no data is received and the scsr1 overrun error flag (bit orer) is set to 1. simultaneous transmit/receive: a simultaneous transmit/receive operation is carried out as follows. 1. set bits so1, si1, and sck1 in pmr2 to 1, selecting the so 1 , si 1 , and sck 1 pin functions. if necessary, set bit pof1 in pmr2 for nmos open drain output at pin so 1 . 2. clear bit snc1 in scr1 to 0, and set bit snc0 to 1 or 0, designating 8- or 16-bit synchronous transfer mode. select the serial clock in bits cks3 to cks0. writing data to scr1 initializes the internal state of sci1. 3. write transmit data in sdrl and sdru, as follows. 8-bit transfer mode: sdrl 16-bit transfer mode: upper byte in sdru, lower byte in sdrl 4. set the scsr1 start flag (stf) to 1. sci1 starts operating. transmit data is output at pin so 1 . receive data is input at pin si 1 . 5. after data transmission and reception are complete, bit irrs1 in irr1 is set to 1. 197 6. read the received data from sdrl and sdru, as follows. 8-bit transfer mode: sdrl 16-bit transfer mode: upper byte in sdru, lower byte in sdrl when an internal clock is used, a serial clock is output from pin sck 1 in synchronization with the transmit data. after data transmission is complete, the serial clock is not output until the next time the start flag is set to 1. during this time, pin so 1 continues to output the value of the last bit transmitted. when an external clock is used, data is transmitted and received in synchronization with the serial clock input at pin sck 1 . after data transmission and reception are complete, an overrun occurs if the serial clock continues to be input; no data is transmitted or received and the scsr1 overrun error flag (bit orer) is set to 1. while transmission is stopped, the output value of pin so 1 can be changed by rewriting bit sol in scsr1. 10.2.4 interrupt sources sci1 can generate an interrupt at the end of a data transfer. when an sci1 transfer is complete, bit irrs1 in interrupt request register 1 (irr1) is set to 1. sci1 interrupt requests can be enabled or disabled by bit iens1 of interrupt enable register 1 (ienr1). for further details, see 3.3, interrupts. 198 10.3 sci3 10.3.1 overview serial communication interface 3 (sci3) has both synchronous and asynchronous serial data communication capabilities. it also has a multiprocessor communication function for serial data communication among two or more processors. features: sci3 features are listed below. selection of asynchronous or synchronous mode ? asynchronous mode serial data communication is performed using the asynchronous method, in which synchronization is achieved character by character. sci3 can communicate with a uart (universal asynchronous receiver/transmitter), acia (asynchronous communication interface adapter), or other chip that employs standard asynchronous serial communication. it can also communicate with two or more other processors using the multiprocessor communication function. there are twelve selectable serial data communication formats. data length: seven or eight bits stop bit length: one or two bits parity: even, odd, or none multiprocessor bit: one or none receive error detection: parity, overrun, and framing errors break detection: by reading the rxd level directly when a framing error occurs ? synchronous mode serial data communication is synchronized with a clock signal. sci3 can communicate with other chips having a clocked synchronous communication function. data length: eight bits receive error detection: overrun errors full duplex communication the transmitting and receiving sections are independent, so sci3 can transmit and receive simultaneously. both sections use double buffering, so continuous data transfer is possible in both the transmit and receive directions. built-in baud rate generator with selectable bit rates. internal or external clock may be selected as the transfer clock source. there are six interrupt sources: transmit end, transmit data register empty, receive data register full, overrun error, framing error, and parity error. 199 block diagram: figure 10.3 shows a block diagram of sci3. sck txd rxd 3 tsr rsr rdr tdr ssr scr3 smr brr brc rsr: rdr: tsr: tdr: smr: scr3: ssr: brr: brc: external clock baud rate generator internal clock (?64, ?16, ?4, ? clock transmit/receive control internal data bus interrupt requests (tei, txi, rxi, eri) legend: receive shift register receive data register transmit shift register transmit data register serial mode register serial control register 3 serial status register bit rate register bit rate counter figure 10.3 sci3 block diagram 200 pin configuration: table 10.4 shows the sci3 pin configuration. table 10.4 pin configuration name abbrev. i/o function sci3 clock sck 3 i/o sci3 clock input/output sci3 receive data input rxd input sci3 receive data input sci3 transmit data output txd output sci3 transmit data output register configuration: table 10.5 shows the sci3 internal register configuration. table 10.5 sci3 registers name abbrev. r/w initial value address serial mode register smr r/w h'00 h'ffa8 bit rate register brr r/w h'ff h'ffa9 serial control register 3 scr3 r/w h'00 h'ffaa transmit data register tdr r/w h'ff h'ffab serial status register ssr r/w h'84 h'ffac receive data register rdr r h'00 h'ffad transmit shift register tsr not possible receive shift register rsr not possible bit rate counter brc not possible 10.3.2 register descriptions receive shift register (rsr) 7 6 5 4 3 0 2 1 bit read/write the receive shift register (rsr) is for receiving serial data. serial data is input in lsb-first order into rsr from pin rxd, converting it to parallel data. after each byte of data has been received, the byte is automatically transferred to the receive data register (rdr). rsr cannot be read or written directly by the cpu. 201 receive data register (rdr) bit 76543210 rdr7 rdr6 rdr5 rdr4 rdr3 rdr2 rdr1 rdr0 initial value 00000000 read/write rrrrrrrr the receive data register (rdr) is an 8-bit register for storing received serial data. each time a byte of data is received, the received data is transferred from the receive shift register (rsr) to rdr, completing a receive operation. thereafter rsr again becomes ready to receive new data. rsr and rdr form a double buffer mechanism that allows data to be received continuously. rdr is exclusively for receiving data and cannot be written by the cpu. rdr is initialized to h'00 upon reset or in standby mode, watch mode, subactive mode, or subsleep mode. transmit shift register (tsr) bit 76543210 read/write the transmit shift register (tsr) is for transmitting serial data. transmit data is first transferred from the transmit data register (tdr) to tsr, then is transmitted from pin txd, starting from the lsb (bit 0). after one byte of data has been sent, the next byte is automatically transferred from tdr to tsr, and the next transmission begins. if no data has been written to tdr (1 is set in tdre), there is no data transfer from tdr to tsr. tsr cannot be read or written directly by the cpu. 202 transmit data register (tdr) bit 76543210 tdr7 tdr6 tdr5 tdr4 tdr3 tdr2 tdr1 tdr0 initial value 11111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w the transmit data register (tdr) is an 8-bit register for holding transmit data. when sci3 detects that the transmit shift register (tsr) is empty, it shifts transmit data written in tdr to tsr and starts serial data transmission. while tsr is transmitting serial data, the next byte to be transmitted can be written to tdr, realizing continuous transmission. tdr can be read or written by the cpu at all times. tdr is initialized to h'ff upon reset or in standby mode, watch mode, subactive mode, or subsleep mode. serial mode register (smr) bit 76543210 com chr pe pm stop mp cks1 cks0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w the serial mode register (smr) is an 8-bit register for setting the serial data communication format and for selecting the clock source of the baud rate generator. smr can be read and written by the cpu at any time. smr is initialized to h'00 upon reset or in standby mode, watch mode, subactive mode, or subsleep mode. bit 7?ommunication mode (com): bit 7 selects asynchronous mode or synchronous mode as the serial data communication mode. bit 7: com description 0 asynchronous mode (initial value) 1 synchronous mode 203 bit 6?haracter length (chr): bit 6 selects either 7 bits or 8 bits as the data length in asynchronous mode. in synchronous mode the data length is always 8 bits regardless of the setting here. bit 6: chr description 0 8-bit data (initial value) 1 7-bit data * note: * when 7-bit data is selected as the character length in asynchronous mode, the msb (bit 7) in the transmit data register is not transmitted. bit 5?arity enable (pe): in asynchronous mode, bit 5 selects whether or not a parity bit is to be added to transmitted data and checked in received data. in synchronous mode there is no adding or checking of parity regardless of the setting here. bit 5: pe description 0 parity bit adding and checking disabled (initial value) 1 parity bit adding and checking enabled * note: * when pe is set to 1, then either odd or even parity is added to transmit data, depending on the setting of the parity mode bit (pm). when data is received, it is checked for odd or even parity as designated in bit pm. bit 4?arity mode (pm): in asynchronous mode, bit 4 selects whether odd or even parity is to be added to transmitted data and checked in received data. the setting here is valid only if parity adding/checking is enabled in bit pe. in synchronous mode, or if parity adding/checking is disabled in asynchronous mode, bit pm is ignored. bit 4: pm description 0 even parity * 1 (initial value) 1 odd parity * 2 notes: 1. when even parity is designated, a parity bit is added to the transmitted data so that the sum of 1s in the resulting data is an even number. when data is received, the sum of 1s in the data plus parity bit is checked to see if the result is an even number. 2. when odd parity is designated, a parity bit is added to the transmitted data so that the sum of 1s in the resulting data is an odd number. when data is received, the sum of 1s in the data plus parity bit is checked to see if the result is an odd number. 204 bit 3?top bit length (stop): bit 3 selects 1 bit or 2 bits as the stop bit length in asynchronous mode. this setting is valid only in asynchronous mode. in synchronous mode a stop bit is not added, so this bit is ignored. bit 3: stop description 0 1 stop bit * 1 (initial value) 1 2 stop bits * 2 notes: 1. when data is transmitted, one ??bit is added at the end of each transmitted character as the stop bit. 2. when data is transmitted, two ??bits are added at the end of each transmitted character as the stop bits. when data is received, only the first stop bit is checked regardless of the stop bit length. if the second stop bit value is 1 it is treated as a stop bit; if it is 0, it is treated as the start bit of the next character. bit 2?ultiprocessor mode (mp): bit 2 enables or disables the multiprocessor communication function. when the multiprocessor communication function is enabled, the parity enable (pe) and parity mode (pm) settings are ignored. the mp bit is valid only in asynchronous mode; it should be cleared to 0 in synchronous mode. see 10.3.6, for details on the multiprocessor communication function. bit 2: mp description 0 multiprocessor communication function disabled (initial value) 1 multiprocessor communication function enabled bits 1 and 0?lock select 1, 0 (cks1, cks0): bits 1 and 0 select the clock source for the built- in baud rate generator. a choice of ?64, ?16, ?4, or ?is made in these bits. see 8, bit rate register, below for information on the clock source and bit rate register settings, and their relation to the baud rate. bit 1: cks1 bit 0: cks0 description 0 0 clock (initial value) 1 ?4 clock 1 0 ?16 clock 1 ?64 clock 205 serial control register 3 (scr3) bit 76543210 tie rie te re mpie teie cke1 cke0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w serial control register 3 (scr3) is an 8-bit register that controls sci3 transmit and receive operations, enables or disables serial clock output in asynchronous mode, enables or disables interrupts, and selects the serial clock source. scr3 can be read and written by the cpu at any time. scr3 is initialized to h'00 upon reset or in standby mode, watch mode, subactive mode, or subsleep mode. bit 7?ransmit interrupt enable (tie): bit 7 enables or disables the transmit data empty interrupt request (txi) when data is transferred from tdr to tsr and the transmit data register empty bit (tdre) in the serial status register (ssr) is set to 1. the txi interrupt can be cleared by clearing bit tdre to 0, or by clearing bit tie to 0. bit 7: tie description 0 transmit data empty interrupt request (txi) disabled (initial value) 1 transmit data empty interrupt request (txi) enabled bit 6?eceive interrupt enable (rie): bit 6 enables or disables the receive error interrupt request (eri), and the receive data full interrupt request (rxi) when data is transferred from rsr to rdr and the receive data register full bit (rdrf) in the serial status register (ssr) is set to 1. receive errors include overrun errors, framing errors, and parity errors. rxi and eri interrupts can be cleared by clearing ssr flag rdrf, or flags fer, per, and oer to 0, or by clearing bit rie to 0. bit 6: rie description 0 receive data full interrupt request (rxi) and receive error interrupt request (eri) disabled (initial value) 1 receive data full interrupt request (rxi) and receive error interrupt request (eri) enabled 206 bit 5?ransmit enable (te): bit 5 enables or disables the start of a transmit operation. bit 5: te description 0 transmit operation disabled * 1 (txd is the transmit data pin) (initial value) 1 transmit operation enabled * 2 (txd is the transmit data pin) notes: 1. the transmit data register empty bit (tdre) in the serial status register (ssr) is fixed at 1. transmit operations are disabled, but the txd pin functions as the transmit data pin. to use the txd pin as an i/o pin, clear bit txd in pmr6 to 0. 2. in this state, writing transmit data in tdr clears bit tdre in ssr to 0 and starts serial data transmission. before setting te to 1 it is necessary to set the transmit format in smr. bit 4?eceive enable (re): bit 4 enables or disables the start of a receive operation. bit 4: re description 0 receive operation disabled * 1 (rxd is a general i/o port) (initial value) 1 receive operation enabled * 2 (rxd is the receive data pin) notes: 1. when re is cleared to 0, this has no effect on the ssr flags rdrf, fer, per, and oer, which retain their states. 2. serial data receiving begins when, in this state, a start bit is detected in asynchronous mode, or serial clock input is detected in synchronous mode. before setting re to 1 it is necessary to set the receive format in smr. bit 3?ultiprocessor interrupt enable (mpie): bit 3 enables or disables multiprocessor interrupt requests. this setting is valid only in asynchronous mode, and only when the multiprocessor mode bit (mp) in the serial mode register (smr) is set to 1. it applies only to data receiving. this bit is ignored when com is set to 1 or when bit mp is cleared to 0. bit 3: mpie description 0 multiprocessor interrupt request disabled (ordinary receive operation) (initial value) [clearing condition] multiprocessor bit receives a data value of 1 1 multiprocessor interrupt request enabled * note: * sci3 does not transfer receive data from rsr to rdr, does not detect receive errors, and does not set status flags rdrf, fer, and oer in ssr. until a multiprocessor bit value of 1 is received, the receive data full interrupt (rxi) and receive error interrupt (eri) are disabled and serial status register (ssr) flags rdrf, fer, and oer are not set. when the multiprocessor bit receives a 1, the mpbr bit of ssr is set to 1, mpie is automatically cleared to 0, rxi and eri interrupts are enabled (provided bits tie and rie in scr3 are set to 1), and setting of the rdrf, fer, and oer flags is enabled. 207 bit 2?ransmit end interrupt enable (teie): bit 2 enables or disables the transmit end interrupt (tei) requested if there is no valid transmit data in tdr when the msb is transmitted. bit 2: teie description 0 transmit end interrupt (tei) disabled (initial value) 1 transmit end interrupt (tei) enabled * note: * a tei interrupt can be cleared by clearing the ssr bit tdre to 0 and clearing the transmit end bit (tend) to 0, or by clearing bit teie to 0. bits 1 and 0?lock enable 1, 0 (cke1, cke0): bits 1 and 0 select the clock source and enable or disable clock output at pin sck 3 . the combination of bits cke1 and cke0 determines whether pin sck 3 is a general i/o port, a clock output pin, or a clock input pin. note that the cke0 setting is valid only when operation is in asynchronous mode using an internal clock (cke1 = 0). this bit is invalid in synchronous mode or when using an external clock (cke1 = 1). in synchronous mode and in external clock mode, clear cke0 to 0. after setting bits cke1 and cke0, the operation mode must first be set in the serial mode register (smr). see table 10.10 in 10.3.3, operation, for details on clock source selection. description bit 1: cke1 bit 0: cke0 communication mode clock source sck 3 pin function 0 0 asynchronous internal clock i/o port * 1 synchronous internal clock serial clock output * 1 1 asynchronous internal clock clock output * 2 synchronous reserved reserved 1 0 asynchronous external clock clock input * 3 synchronous external clock serial clock input 1 asynchronous reserved reserved synchronous reserved reserved notes: 1. initial value 2. a clock is output with the same frequency as the bit rate. 3. input a clock with a frequency 16 times the bit rate. 208 serial status register (ssr) bit 76543210 tdre rdrf oer fer per tend mpbr mpbt initial value 10000100 read/write r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r r r/w note: * only a write of 0 for flag clearing is possible. the serial status register (ssr) is an 8-bit register containing status flags for indicating sci3 states, and containing the multiprocessor bits. ssr can be read and written by the cpu at any time, but the cpu cannot write a 1 to the status flags tdre, rdrf, oer, per, and fer. to clear these flags to 0 it is first necessary to read a 1. bit 2 (tend) and bit 1 (mpbr) are read-only bits and cannot be modified. ssr is initialized to h'84 upon reset or in standby mode, watch mode, subactive mode, or subsleep mode. bit 7?ransmit data register empty (tdre): bit 7 is a status flag indicating that data has been transferred from tdr to tsr. bit 7: tdre description 0 indicates that transmit data written to tdr has not been transferred to tsr [clearing conditions] after reading tdre = 1, cleared by writing 0 to tdre. when data is written to tdr by an instruction. 1 indicates that no transmit data has been written to tdr, or the transmit data written to tdr has been transferred to tsr (initial value) [setting conditions] when bit te in scr3 is cleared to 0. when data is transferred from tdr to tsr. 209 bit 6?eceive data register full (rdrf): bit 6 is a status flag indicating whether there is receive data in rdr. bit 6: rdrf description 0 indicates there is no receive data in rdr (initial value) [clearing conditions] after reading rdrf = 1, cleared by writing 0 to rdrf. when data is read from rdr by an instruction. 1 indicates that there is receive data in rdr [setting condition] when receiving ends normally, with receive data transferred from rsr to rdr note: if a receive error is detected during data receiving, or if bit re in serial control register 3 (scr3) is cleared to 0, rdr and rdrf are unaffected and keep their previous states. an overrun error (oer) occurs if receiving of data is completed while bit rdrf remains set to 1. if this happens, receive data will be lost. bit 5?verrun error (oer): bit 5 is a status flag indicating that an overrun error has occurred during data receiving. bit 5: oer description 0 indicates that data receiving is in progress or has been completed * 1 (initial value) [clearing condition] after reading oer = 1, cleared by writing 0 to oer 1 indicates that an overrun error occurred in data receiving * 2 [setting condition] when data receiving is completed while rdrf is set to 1 notes: 1. when bit re in serial control register 3 (scr3) is cleared to 0, oer is unaffected and keeps its previous state. 2. rdr keeps the data received prior to the overrun; data received after that is lost. while oer is set to 1, data receiving cannot be continued. in synchronous mode, data transmitting cannot be continued either. 210 bit 4: framing error (fer): bit 4 is a status flag indicating that a framing error has occurred during asynchronous receiving. bit 4: fer description 0 indicates that data receiving is in progress or has been completed * 1 (initial value) [clearing condition] after reading fer = 1, cleared by writing 0 to fer 1 indicates that a framing error occurred in data receiving [setting condition] the stop bit at the end of receive data is checked and found to be 0 * 2 notes: 1. when bit re in serial control register 3 (scr3) is cleared to 0, fer is unaffected and keeps its previous state. 2. when two stop bits are used only the first stop bit is checked, not the second. when a framing error occurs, receive data is transferred to rdr but rdrf is not set. while fer is set to 1, data receiving cannot be continued. in synchronous mode, data transmission and reception cannot be performed if fer is set to 1. bit 3?arity error (per): bit 3 is a status flag indicating that a parity error has occurred during asynchronous receiving. bit 3: per description 0 indicates that data receiving is in progress or has been completed * 1 (initial value) [clearing condition] after reading per = 1, cleared by writing 0 to per 1 indicates that a parity error occurred in data receiving * 2 [setting condition] when the sum of 1s in received data plus the parity bit does not match the parity mode bit (pm) setting in the serial mode register (smr) notes: 1. when bit re in serial control register 3 (scr3) is cleared to 0, per is unaffected and keeps its previous state. 2. when a parity error occurs, receive data is transferred to rdr but rdrf is not set. while per is set to 1, data receiving cannot be continued. while per is set to 1 in synchronous mode, data transmission and reception cannot be performed. 211 bit 2?ransmit end (tend): bit 2 is a status flag indicating that tdre was set to 1 when the last bit of a transmitted character was sent. tend is a read-only bit and cannot be modified. bit 2: tend description 0 indicates that transmission is in progress [clearing conditions] after reading tdre = 1, cleared by writing 0 to tdre. when data is written to tdr by an instruction. 1 indicates that a transmission has ended (initial value) [setting conditions] when bit te in scr3 is cleared to 0. if tdre is set to 1 when the last bit of a transmitted character is sent. bit 1?ultiprocessor bit receive (mpbr): bit 1 holds the multiprocessor bit in data received in asynchronous mode using a multiprocessor format. mpbr is a read-only bit and cannot be modified. bit 1: mpbr description 0 indicates reception of data in which the multiprocessor bit is 0 * (initial value) 1 indicates reception of data in which the multiprocessor bit is 1 note: * if bit re in scr3 is cleared to 0 while a multiprocessor format is in use, mpbr retains its previous state. bit 0?ultiprocessor bit transmit (mpbt): bit 0 holds the multiprocessor bit to be added to transmitted data when a multiprocessor format is used in asynchronous mode. bit mpbt is ignored when synchronous mode is chosen, when the multiprocessor communication function is disabled, or when data transmission is disabled. bit 0: mpbt description 0 the multiprocessor bit in transmit data is 0 (initial value) 1 the multiprocessor bit in transmit data is 1 212 bit rate register (brr) bit 76543210 brr7 brr6 brr5 brr4 brr3 brr2 brr1 brr0 initial value 11111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w the bit rate register (brr) is an 8-bit register which, together with the baud rate generator clock selected by bits cks1 and cks0 in the serial mode register (smr), sets the transmit/receive bit rate. brr can be read or written by the cpu at any time. brr is initialized to h'ff upon reset or in standby mode, watch mode, subactive mode, or subsleep mode. table 10.6 gives examples of how brr is set in asynchronous mode. the values in table 10.6 are for active (high-speed) mode. 213 table 10.6 brr settings and bit rates in asynchronous mode osc (mhz) 2 2.4576 4 4.194304 bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 1 70 +0.03 1 86 +0.31 1 141 +0.03 1 148 ?.04 150 0 207 +0.16 0 255 0 1 103 +0.16 1 108 +0.21 300 0 103 +0.16 0 127 0 0 207 +0.16 0 217 +0.21 600 0 51 +0.16 0 63 0 0 103 +0.16 0 108 +0.21 1200 0 25 +0.16 0 31 0 0 51 +0.16 0 54 ?.70 2400 0 12 +0.16 0 15 0 0 25 +0.16 0 26 +1.14 4800 0 7 0 0 12 +0.16 0 13 ?.48 9600 0 3 0 0 6 ?.48 19200 0 1 0 31250 0 0 0 0 1 0 38400 0 0 0 table 10.6 brr settings and bit rates in asynchronous mode (cont) osc (mhz) 4.9152 6 7.3728 8 bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 1 174 ?.26 1 212 +0.03 2 64 +0.70 2 70 +0.03 150 1 127 0 1 155 +0.16 1 191 0 1 207 +0.16 300 0 255 0 1 77 +0.16 1 95 0 1 103 +0.16 600 0 127 0 0 155 +0.16 0 191 0 0 207 +0.16 1200 0 63 0 0 77 +0.16 0 95 0 0 103 +0.16 2400 0 31 0 0 38 +0.16 0 47 0 0 51 +0.16 4800 0 15 0 0 19 ?.34 0 23 0 0 25 +0.16 9600 0 7 0 0 9 ?.34 0 11 0 0 12 +0.16 19200 0 3 0 0 4 ?.34 0 5 0 31250 0 2 0 0 3 0 38400 0 1 0 0 2 0 214 table 10.6 brr settings and bit rates in asynchronous mode (cont) osc (mhz) 9.8304 10 bit rate (bits/s) n n error (%) n n error (%) 110 2 86 +0.31 2 88 ?.25 150 1 255 0 2 64 +0.16 300 1 127 0 1 129 +0.16 600 0 255 0 1 64 +0.16 1200 0 127 0 0 129 +0.16 2400 0 63 0 0 64 +0.16 4800 0 31 0 0 32 ?.36 9600 0 15 0 0 15 +1.73 19200 0 7 0 0 7 +1.73 31250 0 4 ?.70 0 4 0 38400 0 3 0 0 3 +1.73 notes: 1. settings should be made so that error is within 1%. 2. brr setting values are derived by the following equation. n = 10 6 ?1 osc 64 2 2n b b: bit rate (bits/s) n: brr baud rate generator setting (0 n 255) osc: value of osc (mhz) n: baud rate generator input clock number (n = 0, 1, 2, 3) the meaning of n is shown in table 10.7. table 10.7 relation between n and clock smr setting n clock cks1 cks0 0 0 0 1 ?4 0 1 2 ?6 1 0 3 ?64 1 1 215 3. the error values in table 10.6 were derived by performing the following calculation and rounding off to two decimal places. error (%) = 100 b ?r r b: bit rate found from n, n, and osc r: bit rate listed in left column of table 10.6 table 10.8 shows the maximum bit rate for selected frequencies in asynchronous mode. values in table 10.8 are for active (high-speed) mode. table 10.8 maximum bit rate at selected frequencies (asynchronous mode) setting osc (mhz) maximum bit rate (bits/s) n n 2 31250 0 0 2.4576 38400 0 0 4 62500 0 0 4.194304 65536 0 0 4.9152 76800 0 0 6 93750 0 0 7.3728 115200 0 0 8 125000 0 0 9.8304 153600 0 0 10 156250 0 0 table 10.9 shows typical brr settings in synchronous mode. values in table 10.9 are for active (high-speed) mode. 216 table 10.9 typical brr settings and bit rates (synchronous mode) osc (mhz) bit rate 24810 (bits/s) n n n n n n n n 110 250 1 249 2 124 2 249 500 1 124 1 249 2 124 1k 0 249 1 124 1 249 2.5k 0 99 0 199 1 99 1 124 5k 0 49 0 99 0 199 0 249 10k 0 24 0 49 0 99 0 124 25k 0 9 0 19 0 39 0 49 50k 0 4 0 9 0 19 0 24 100k 0 4 0 9 250k 0 0 * 01 03 04 500k 0 0 * 01 1m 0 0 * 2.5m blank: cannot be set ? can be set, but error will result * : continuous transmit/receive operation is not possible at this setting note: brr setting values are derived by the following equation. n = 10 6 ?1 osc 8 2 2n b b: bit rate (bits/s) n: brr baud rate generator setting (0 n 255) osc: value of osc (mhz) n: baud rate generator input clock number (n = 0, 1, 2, 3) the meaning of n is shown in table 10.10. 217 table 10.10 relation between n and clock smr setting n clock cks1 cks0 0 0 0 1 ?4 0 1 2 ?6 1 0 3 ?64 1 1 10.3.3 operation sci3 supports serial data communication in both asynchronous mode, where each character transferred is synchronized separately, and synchronous mode, where transfer is synchronized by clock pulses. the choice of asynchronous mode or synchronous mode, and the communication format, is made in the serial mode register (smr), as shown in table 10.11. the sci3 clock source is determined by bit com in smr and bits cke1 and cke0 in serial control register 3 (scr3), as shown in table 10.12. asynchronous mode: data length: choice of 7 bits or 8 bits choice for the addition of a parity bit, the multiprocessor bit as well as one or two stop bits (these options determine the transmit/receive format and the character length). framing error (fer), parity error (per), overrun error (oer), and break signal can be detected when data is received. clock source: choice of internal clocks or an external clock ? when an internal clock is selected: operates on baud rate generator clock. a clock can be output with the same frequency as the bit rate. ? when an external clock is selected: a clock input with a frequency 16 times the bit rate is required (internal baud rate generator is not used). synchronous mode: transfer format: 8 bits overrun errors can be detected when data is received. clock source: choice of internal clocks or an external clock ? when an internal clock is selected: operates on baud rate generator clock, and outputs a serial clock. 218 ? when an external clock is selected: the internal baud rate generator is not used. operation is synchronous with the input clock. table 10.11 smr settings and sci3 communication format smr setting communication format bit 7: com bit 6: chr bit 2: mp bit 5: pe bit 3: stop mode data length multipro- cessor bit parity bit stop bit length 00000 asynchronous 8-bit data none none 1 bit 1 mode 2 bits 1 0 yes 1 bit 1 2 bits 1 0 0 7-bit data none 1 bit 1 2 bits 1 0 yes 1 bit 1 2 bits 01 * 0 asynchronous 8-bit data yes none 1 bit * 1 mode 2 bits 1 * 0 (multiprocessor 7-bit data 1 bit * 1 format) 2 bits 1 * 0 ** synchronous mode 8-bit data none none none note: * don? care 219 table 10.12 smr and scr3 settings and clock source selection smr scr3 transmit/receive clock bit 7: com bit 1: cke1 bit 0: cke0 mode clock source pin sck 3 function 0 0 0 asynchronous internal i/o port (sck 3 pin not used) 1 mode outputs clock with same frequency as bit rate 1 0 external clock should be input with frequency 16 times the desired bit rate 1 0 0 synchronous internal outputs a serial clock 10 mode external inputs a serial clock 0 1 1 reserved (illegal settings) 101 111 220 continuous transmit/receive operation using interrupts: continuous transmit and receive operations are possible with sci3, using the rxi or txi interrupts. table 10.13 explains this use of these interrupts. table 10.13 transmit/receive interrupts interrupt flag interrupt conditions remarks rxi rdrf rie when serial data is received normally and receive data is transferred from rsr to rdr, rdrf is set to 1. if rie is 1 at this time, rxi is enabled and an interrupt occurs. (see figure 10.4 (a).) the rxi interrupt handling routine reads the receive data from rdr and clears rdrf to 0. cont i nuous dat a recept ion is poss i ble by performing these operations before the reception of the next serial data in rsr is completed. txi tdre tie when tsr empty (previous transmission complete) is detected and the transmit data set in tdr is transferred to tsr, tdre is set to 1. if tie is 1 at this time, txi is enabled and an interrupt occurs. (see figure 10.4 (b).) the txi interrupt handling routine writes the next transmit data to tdr and clears tdre to 0. continuous data transmission is possible by performing these operations before the transmission of data transferred to tsr is completed. tei tend teie when the last bit of the tsr transmit character has been sent, if tdre is 1, then 1 is set in tend. if teie is 1 at this time, tei is enabled and an interrupt occurs. (see figure 10.4 (c).) tei indicates that, when the last bit of the tsr transmit character was sent, the next transmit data had not been written to tdr. 221 rdr rsr (receiving) rxd pin rdrf = 0 rdr rsr (received and transferred) rxd pin rdrf 1 (rxi requested if rie = 1) ? - figure 10.4 (a) rdrf setting and rxi interrupt tdr (next transmit data) tsr (transmitting) txd pin tdre = 0 tdr tsr (transmission complete, next data transferred) txd pin tdre 1 (txi requested if tie = 1) ? figure 10.4 (b) tdre setting and txi interrupt tdr tsr (transmitting) txd pin tend = 0 tdr tsr (transmission complete) txd pin tend 1 (tei requested if teie = 1) ? figure 10.4 (c) tend setting and tei interrupt 222 10.3.4 operation in asynchronous mode in asynchronous communication mode, a start bit indicating the start of communication and a stop bit indicating the end of communication are added to each character that is sent/received. in this way synchronization is achieved for each character as a self-contained unit. sci3 consists of independent transmit and receive modules, giving it the capability of full duplex communication. both the transmit and receive modules have a double-buffer configuration, allowing data to be read or written during communication operations so that data can be transmitted and received continuously. (1) transmit/receive formats: figure 10.5 shows the general format for asynchronous serial communication. the communication line in asynchronous communication mode normally stays at the high level, in the ?ark?state. sci3 monitors the communication line, and begins serial data communication when it detects a ?pace?(low-level signal), which is regarded as a start bit. one character consists of a start bit (low level), transmit/receive data (in lsb-first order), a parity bit (high or low level), and finally a stop bit (high level), in this order. in asynchronous data receiving, synchronization is carried out at the falling edge of the start bit. sci3 samples data on the 8th pulse of a clock that has 16 times the frequency of one-bit interval, so each bit of data is latched at its center. serial data one unit of data (character or frame) start bit transmit or receive data parity bit (msb) stop bit 1 bit 1 bit or none 1 or 2 bits 7 or 8 bits mark state (lsb) 1 figure 10.5 data format in asynchronous serial communication mode 223 table 10.14 shows the 12 formats that can be selected in asynchronous mode. the format is selected in the serial mode register (smr). table 10.14 serial communication formats in asynchronous mode smr settings serial communication format and frame length chr pe mp stop 123456789101112 0000 s 8-bit data stop 0001 s 8-bit data stop stop 0100 s 8-bit data p stop 0101 s 8-bit data p stop stop 1000 s 7-bit data stop 1001 s 7-bit data stop stop 1100 s 7-bit data p stop 1101 s 7-bit data p stop stop 0 * 1 0 s 8-bit data mpb stop 0 * 1 1 s 8-bit data mpb stop stop 1 * 1 0 s 7-bit data mpb stop 1 * 1 1 s 7-bit data mpb stop stop legend: s: start bit stop: stop bit p: parity bit mpb: multiprocessor bit note: * don? care 224 (2) clock: the clock source is determined by bit com in smr and bits cke1 and cke0 in serial control register 3 (scr3). see table 10.12 for the settings. either an internal clock source can be used to run the built-in baud rate generator, or an external clock source can be input at pin sck 3 . when an external clock source is input to pin sck 3 , it should have a frequency 16 times the desired bit rate. when an internal clock source is used, sck 3 can be used as the clock output pin. the clock output has the same frequency as the serial bit rate, and is synchronized as in figure 10.6 so that the rising edge of the clock occurs in the center of each bit of transmit/receive data. serial data 1 character (1 frame) 0 d0d1d2d3d4d5d6d70/1 1 1 clock figure 10.6 phase relation of output clock and communication data in asynchronous mode (8-bit data, parity bit added, and 2 stop bits) (3) data transmit/receive operations sci3 initialization: before data is sent or received, bits te and re in serial control register 3 (scr3) must be cleared to 0, after which initialization can be performed using the procedure. note: when modifying the operation mode, transfer format or other settings, always be sure to clear bits te and re first. when te is cleared to 0, bit tdre will be set to 1. clearing re does not clear the status flags rdrf, per, fer, or oer, or alter the contents of the receive data register (rdr). when an external clock is used in asynchronous mode, do not stop the clock during operation, including during initialization. 225 figure 10.7 shows a typical flow chart for sci3 initialization. start clear te and re to 0 in scr3 select communication format in smr set brr value has a 1-bit interval elapsed? set bits rie, tie, teie, and mpie in scr3, and set te or re to 1 2 3 4 2. 3. 4. 1. set the transmit/receive format in the serial mode register (smr). write the value corresponding to the desired bit rate to the bit rate register (brr). note that this setting is not required when using an external clock. wait for at least a 1-bit interval, then set bits rie, tie, teie, and mpie, and set bit te or re in scr3 to 1. setting te or re no yes wait end enables sci3 to use the txd or rxd pin. the initial states in asynchronous mode are the mark transmit state and the idle receive state (waiting for a start bit). 1 set bits cke1 and cke0 select the clock using serial control register 3(scr3). be sure to set 0 for other unused bits. when the clock output is selected in the asynchronous mode, a clock signal is output immediately after setting bits cke1 and cke0 appropriately. figure 10.7 typical flow chart when sci3 is initialized 226 transmitting: figure 10.8 shows a typical flow chart for data transmission. after sci3 initialization, follow the procedure below. start read bit tdre in ssr tdre = 1? write transmit data in tdr continue data transmission? tend = 1? read bit tend in ssr break output? set pdr = 0 and pcr = 1 clear bit te in scr3 to 0 end 1 2 3 1. 2. 3. read the serial status register (srr), and after confirming that bit tdre = 1, write transmit data in the transmit data register (tdr). when data is written to tdr, tdre is automatically cleared to 0. to continue transmitting data, first read tdre to confirm that it is set to 1, indicating that data writing is enabled, then write the next data to tdr. when data is written to tdr, tdre is automatically cleared to 0. to output a break signal when transmission ends, first set the port values pcr = 1 and pdr = 0, then clear bit te in scr3 to 0. no yes no no yes no yes yes figure 10.8 typical data transmission flow chart (asynchronous mode) 227 sci3 operates as follows during data transmission in asynchronous mode. sci3 monitors bit tdre in ssr. when this bit is cleared to 0, sci3 recognizes that there is data written in the transmit data register (tdr), which it transfers to the transmit shift register (tsr). then tdre is set to 1 and transmission starts. if bit tie in scr3 is set to 1, a txi interrupt is requested. serial data is transmitted from pin txd using the communication format outlined in table 10.14. after that, it checks tdre at the same timing which it transmits the stop bit. if tdre is 0, data is transferred from tdr to tsr, and after the stop bit is sent, transmission of the next frame starts. if tdre is 1, the tend bit in ssr is set to 1, and after the stop bit is sent, the ?ark state?is entered, in which 1 is continuously output. a tei interrupt is requested in this state if bit teie in scr3 is set to 1. figure 10.9 shows a typical operation in asynchronous transmission mode. 0 d0 d1 d7 0/1 1 d0 d1 d7 0/1 1 0 start bit parity bit stop bit parity bit stop bit 1 start bit mark state tdre tend txi request tei request 1 frame txi request serial data transmit data transmit data 1 frame sci3 operation user processing tdre cleared to 0 1 write data in tdr figure 10.9 typical transmit operation in asynchronous mode (8-bit data, parity bit added, and 1 stop bit) receiving: figure 10.10 shows a typical flow chart for receiving serial data. after sci3 initialization, follow the procedure below. 228 start read bits oer, per, and fer in ssr read bit rdrf in ssr continue receiving? clear bit re in scr3 to 0 end 1 yes yes no no 1. read bits oer, per, and fer in the serial status register (ssr) to determine if a receive error has occurred. if a receive error has occurred, receive error processing is executed. oer = 1? fer = 1? per = 1? clear bits oer, per, and fer in ssr to 0 overrun error processing break? framing error processing parity error processing yes yes yes no no no yes no 4 receive error processing end receive error processing 4 a start receive error processing a oer + per + fer = 1 rdrf = 1? no yes 2. read the serial status register (ssr), and after confirming that bit rdrf = 1, read received data from the receive data register (rdr). when rdr data is read, rdrf is automatically cleared to 0. 3. to continue receiving data, read bit rdrf and finish reading rdr before the stop bit of the present frame is received. when data is read from rdr, rdrf is automatically cleared to 0. 4. when a receive error occurs, read bits oer, per, and fer in ssr to determine which error (s) occurred. after the necessary error processing, be sure to clear the above bits all to 0. data receiving cannot be resumed while any of bits oer, per, or fer is set to 1. when a framing error occurs, a break can be detected by reading the rxd pin value. 2 read received data in rdr 3 figure 10.10 typical serial data receiving flow chart in asynchronous mode 229 sci3 operates as follows when receiving serial data in asynchronous mode. sci3 monitors the communication line, and when a start bit (0) is detected it performs internal synchronization and starts receiving. the communication format for data receiving is as outlined in table 10.14. received data is set in rsr in order of lsb to msb, then the parity bit and stop bit(s) are received. after receiving the data, sci3 performs the following checks: parity check: the number of 1s in receive data is checked to see if it matches the odd or even parity selected in bit pm of smr. stop bit check: the stop bit is checked for a value of 1. if there are two stop bits, only the first bit is checked. status check: the rdrf bit is checked for a value of 0 to make sure received data can be transferred from rsr to rdr. if no receive error is detected by the above checks, bit rdrf is set to 1 and the received data is stored in rdr. at that time, if bit rie in scr3 is set to 1, an rxi interrupt is requested. if the error check detects a receive error, the appropriate error flag (oer, per, or fer) is set to 1. rdrf retains the same value as before the data was received. if at this time bit rie in scr3 is set to 1, an eri interrupt is requested. table 10.15 gives the receive error detection conditions and the processing of received data in each case. note: data receiving cannot be continued while a receive error flag is set. before continuing the receive operation it is necessary to clear the oer, fer, per, and rdrf flags to 0. table 10.15 receive error conditions and received data processing receive error abbrev. detection conditions received data processing overrun error oer receiving of the next data ends while bit rdrf in ssr is still set to 1 received data is not transferred from rsr to rdr framing error fer stop bit is 0 received data is transferred from rsr to rdr parity error per received data does not match the parity (odd/even) set in smr received data is transferred from rsr to rdr 230 figure 10.11 shows a typical sci3 data receive operation in asynchronous mode. 0 d0 d1 d7 0/1 1 d0 d1 d7 0/1 0 0 start bit parity bit stop bit parity bit stop bit 1 start bit mark (idle state) rdrf fer 1 frame serial data rxi request detects stop bit = 0 eri request due to framing error 1 frame 1 sci3 operation receive data receive data read rdr data user processing rdrf cleared to 0 framing error handling figure 10.11 typical receive operation in asynchronous mode (8-bit data, parity bit added, and 1 stop bit) 10.3.5 operation in synchronous mode in synchronous mode, data is sent or received in synchronization with clock pulses. this mode is suited to high-speed serial communication. sci3 consists of independent transmit and receive modules, so full duplex communication is possible, sharing the same clock between both modules. both the transmit and receive modules have a double-buffer configuration. this allows data to be written during a transmit operation so that data can be transmitted continuously, and enables data to be read during a receive operation so that data can be received continuously. 231 (1) transmit/receive format: figure 10.12 shows the general communication data format for synchronous communication. note: at high level except during continuous transmit/receive. serial data serial clock one unit of communication data (character or frame) bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 don't care don't care * * * lsb msb 8 bits figure 10.12 data format in synchronous communication mode in synchronous communication, data is output to the communication line during the period from one falling edge of the synchronous clock to the next falling edge. data fixing is guaranteed at the rising edge of the synchronous clock. one character of data starts from the lsb and ends with the msb. the communication line retains the msb state after the msb is output. in synchronous receive mode, sci3 latches receive data in synchronization with the rising edge of the serial clock. the transmit/receive format is fixed at 8-bit data. no parity bit or multiprocessor bit is added in this mode. (2) clock: either an internal clock from the built-in baud rate generator is used, or an external clock is input at pin sck 3 . the choice of clock sources is designated by bit com in smr and bits cke1 and cke0 in serial control register 3 (scr3). see table 10.12 for details on selecting the clock source. when operation is based on an internal clock, a serial clock is output at pin sck 3 . eight clock pulses are output per character of transmit/receive data. when no transmit or receive operation is being performed, the pin is held at the high level. (3) data transmit/receive operations sci3 initialization: before data is sent or received, bits te and re in serial control register 3 (scr3) must be cleared to 0, after which initialization can be performed using the procedure. 232 note: when modifying the operation mode, transfer format or other settings, always be sure to clear bits te and re first. when te is cleared to 0, bit tdre will be set to 1. clearing re does not clear the status flags rdrf, per, fer, or oer, or alter the contents of the receive data register (rdr). when an external clock is used in synchronous mode, do not supply the clock during initialization. figure 10.13 shows a typical flow chart for sci3 initialization. start clear te and re to 0 in scr3 select communication format in smr set brr value has a 1-bit interval elapsed? set bits rie, tie, teie, and mpie in scr3, and set te or re to 1 2 3 4 2. 3. 4. 1. set the transmit/receive format in the serial mode register (smr). write the value corresponding to the desired bit rate to the bit rate register (brr). note that this setting is not required when using an external clock. wait for at least a 1-bit interval, then set bits rie, tie, teie, and mpie, and set bit te or re in scr3 to 1. setting te or re note: in simultaneous transmit/receive operations, the te and re bits should both be cleared to 0 or set to 1 simultaneously. no yes wait end enables sci3 to use the txd or rxd pin. the initial states in asynchronous mode are the mark transmit state and the idle receive state (waiting for a start bit). 1 set bits cke1 and cke0 select the clock using serial control register 3(scr3). be sure to set 0 for other unused bits. when the clock output is selected in the asynchronous mode, a clock signal is output immediately after setting bits cke1 and cke0 appropriately. when the clock output is selected in the synchronous mode, a clock signal is output immediately after setting bits cke1 and cke0 appropriately and setting bit re to 1. figure 10.13 typical flow chart when sci3 is initialized 233 transmitting: figure 10.14 shows a typical flow chart for data transmission. after sci3 initialization, follow the procedure below. start read bit tdre in ssr tdre = 1? write transmit data in tdr continue data transmission? read bit tend in ssr tend = 1? write 0 to bit te in scr3 end no yes no yes no yes 1 2 1. 2. read the serial status register (ssr), and after confirming that bit tdre = 1, write transmit data in the transmit data register (tdr). when data is written to tdr, tdre is automatically cleared to 0. if clock output has been selected, after data is written to tdr, the clock is output and data transmission begins. to continue transmitting data, first read tdre to confirm that it is set to 1, indicating that data writing is enabled; then write the next data to tdr. when data is written to tdr, tdre is automatically cleared to 0. figure 10.14 typical data transmission flow chart in synchronous mode 234 sci3 operates as follows during data transmission in synchronous mode. sci3 monitors bit tdre in ssr. when this bit is cleared to 0, sci3 recognizes that there is data written in the transmit data register (tdr), which it transfers to the transmit shift register (tsr). then tdre is set to 1 and transmission starts. if bit tie in scr3 is set to 1, a txi interrupt is requested. if clock output is selected, sci3 outputs eight serial clock pulses. if an external clock is used, data is output in synchronization with the clock input. serial data is transmitted from pin txd in order from lsb (bit 0) to msb (bit 7). after that, it checks tdre at the same timing which it transmits the msb (bit 7). if tdre is 0, data is transferred from tdr to tsr, and after the msb (bit 7) is sent, transmission of the next frame starts. if tdre is 1, the tend bit in ssr is set to 1, and after the msb (bit 7) is sent, the msb state is maintained. a tei interrupt is requested in this state if bit teie in scr3 is set to 1. after data transmission ends, pin sck 3 is held at the high level. note: data transmission cannot take place while any of the receive error flags (oer, fer, per) is set to 1. be sure to confirm that these error flags are cleared to 0 before starting transmission. figure 10.15 shows a typical sci3 transmit operation in synchronous mode. serial clock serial data tdre tend bit 0 bit 7 bit 0 bit 1 bit 6 bit 7 bit 1 txi request tdre cleared to 0 txi request tei request 1 frame 1 frame sci3 operation user processing write data in tdr figure 10.15 typical sci3 transmit operation in synchronous mode 235 receiving: figure 10.16 shows a typical flow chart for receiving data. after sci3 initialization, follow the procedure below. start read bit oer in ssr read bit rdrf in ssr read received data in rdr oer = 1? continue receiving? clear bit re in scr3 to 0 end clear bit oer in ssr to 0 1 3 4 4 2. 3. 4. read the serial status register (ssr), and after confirming that bit rdrf = 1, read received data from the receive data register (rdr). when data is read from rdr, rdrf is automatically cleared to 0. 1. read bit oer in the serial status register (ssr) to determine if an error has occurred. if an overrun error has occurred, overrun error processing is executed. to continue receiving data, read bit rdrf and read the received data in rdr before the msb (bit 7) of the present frame is received. when data is read from rdr, rdrf is automatically cleared to 0. when an overrun error occurs, read bit oer in ssr. after the necessary error processing, be sure to clear oer to 0. data receiving cannot be resumed while bit oer is set to 1. yes yes no no rdrf = 1? no yes overrun error processing start overrun processing end overrun error processing overrun error processing 2 figure 10.16 typical data receiving flow chart in synchronous mode 236 sci3 operates as follows when receiving serial data in synchronous mode. in synchronization with the input or output of the serial clock, sci3 initializes internally and starts receiving. received data is set in rsr from lsb to msb. after data has been received, sci3 checks to confirm that the value of bit rdrf is 0 indicating that received data can be transferred from rsr to rdr. if this check passes, rdrf is set to 1 and the received data is stored in rdr. at this time, if bit rie in scr3 is set to 1, an rxi interrupt is requested. if an overrun error is detected, oer is set to 1 and rdrf remains set to 1. then if bit rie in scr3 is set to 1, an eri interrupt is requested. for the overrun error detection conditions and receive data processing, see table 10.15. note: data receiving cannot be continued while a receive error flag is set. before continuing the receive operation it is necessary to clear the oer, fer, per, and rdrf flags to 0. figure 10.17 shows a typical receive operation in synchronous mode. serial clock serial data rdrf oer sci3 operation user processing bit 7 bit 0 bit 7 bit 0 bit 1 bit 6 bit 7 1 frame 1 frame rxi request rdrf cleared to 0 rxi request read data from rdr eri request due to overrun error rdr data not read (rdrf = 1) overrun error handling figure 10.17 typical receive operation in synchronous mode 237 simultaneous transmit/receive: figure 10.18 shows a typical flow chart for transmitting and receiving simultaneously. after sci3 synchronization, follow the procedure below. start read bit tdre in ssr read rdrf in ssr rdrf = 1? read received data in rdr read bit oer in ssr oer = 1? continue transmitting and receiving? clear bits te and re in scr3 to 0 end 1 1. 2. 3. 4. 4 read the serial status register (ssr), and after confirming that bit tdre = 1, write transmit data in the transmit data register (tdr). when data is written to tdr, tdre is automatically cleared to 0. read the serial status register (ssr), and after confirming that bit rdrf = 1, read the received data from the receive data register (rdr). when data is read from rdr, rdrf is automatically cleared to 0. to continue transmitting and receiving serial data, read bit rdrf and finish reading rdr before the msb (bit 7) of the present frame is received. also read bit when an overrun error occurs, read bit oer in ssr. after the necessary error processing, be sure to clear oer to 0. data transmission and reception cannot take place while bit oer is set to 1. see figure 10.16 for overrun error processing. note: when switching from transmit or receive operation to simultaneous transmit/ receive operations, first clear the te bit and re bit to 0, then set both these bits to 1 simultaneously. tdre = 1? no no yes yes yes no 3 no yes write transmit data in tdr overrun error processing tdre, check that it is set to 1, and write the next data in tdr before the msb (bit 7) of the current frame has been transmitted. when data is written to tdr, tdre is automatically cleared to 0; and when data is read from rdr, rdrf is automatically cleared to 0. 2 figure 10.18 simultaneous transmit/receive flow chart in synchronous mode 238 notes: 1. to switch from transmitting to simultaneous transmitting and receiving, first confirm that tdre and tend are both set to 1 and that sci3 has finished transmitting. next clear te to 0. then set both te and re to 1. 2. to switch from receiving to simultaneous transmitting and receiving, after confirming that sci3 has finished receiving, clear re to 0. next, after confirming that rdrf and the error flags (oer fer, per) are all 0, set both te and re to 1. 10.3.6 multiprocessor communication function the multiprocessor communication function enables several processors to share a single serial communication line. the processors communicate in asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). in multiprocessor communication, each receiving processor is addressed by an id code. a serial communication cycle consists of two cycles: an id-sending cycle that identifies the receiving processor, and a data-sending cycle in which communication data is sent to the specified receiving processor. the multiprocessor bit is used to distinguish between the id-sending cycle and the data-sending cycle. the multiprocessor bit is 1 in an id-sending cycle, and 0 in a data-sending cycle. the transmitting processor starts by sending the id of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. when a receiving processor receives data with the multiprocessor bit set to 1, it compares the data with its own id. if the data matches its id, the receiving processor continues to receive incoming data. if the data does not match its id, the receiving processor skips further incoming data until it again receives data with the multiprocessor bit set to 1. multiple processors can send and receive data in this way. figure 10.19 shows an example of communication among different processors using a multiprocessor format. 239 transmitting processor receiving processor a communication line receiving processor b receiving processor c receiving processor d serial data id-sending cycle (receiving processor address) data-sending cycle (data sent to receiving processor designated by id) (id = 01) (id = 02) (id = 03) (id = 04) h'01 h'aa (mpb = 1) (mpb = 0) mpb: multiprocessor bit figure 10.19 example of interprocessor communication using multiprocessor format (data h'aa sent to receiving processor a) four communication formats are available. parity-bit settings are ignored when a multiprocessor format is selected. for details see table 10.14. for a description of the clock used in multiprocessor communication, see 10.3.4, operation in asynchronous mode. 240 transmitting multiprocessor data: figure 10.20 shows a typical flow chart for multiprocessor serial data transmission. after sci3 initialization, follow the procedure below. start read bit tdre in ssr tdre = 1? set bit mpbt in ssr write transmit data to tdr continue transmitting? read bit tend in ssr tend = 1? break output? set pdr = 0 and pcr = 1 clear bit te in scr3 to 0 end 1 2 3 2. 3. 1. to continue transmitting data, read bit tdre to make sure it is set to 1, indicating that data writing is enabled. then write the next data to tdr. when data is written to tdr, tdre is automatically cleared to 0. to output a break signal at the end of data transmission, first set the port values pcr = 1 and pdr = 0, then clear bit te in scr3 to 0. read the serial status register (ssr), and after confirming that bit tdre = 1, set bit mpbt (multiprocessor bit transmit) in ssr to 0 or 1, then write transmit data in the transmit data register (tdr). no yes no no yes no yes yes when data is written to tdr, tdre is automatically cleared to 0. figure 10.20 typical multiprocessor data transmission flow chart 241 sci3 operates as follows during data transmission using a multiprocessor format. sci3 monitors bit tdre in ssr. when this bit is cleared to 0, sci3 recognizes that there is data written in the transmit data register (tdr), which it transfers to the transmit shift register (tsr). then tdre is set to 1 and transmission starts. if bit tie in scr3 is set to 1, a txi interrupt is requested. serial data is transmitted from pin txd using the communication format outlined in table 10.14. next, tdre is checked as the stop bit is being transmitted. if tdre is 0, data is transferred from tdr to tsr, and after the stop bit is sent, transmission of the next frame starts. if tdre is 1, the tend bit in ssr is set to 1, and after the stop bit is sent the output remains at 1 (mark state). a tei interrupt is requested in this state if bit teie (transmit end interrupt enable) in scr3 is set to 1. figure 10.21 shows a typical sci3 operation in multiprocessor communication mode. 0d0d1 d7 d0 d1 0 d7 1 0/1 1 0/1 start bit start bit stop bit stop bit mpb mpb 1 tdre tend tdre cleared to 0 txi request tei request 1 frame txi request serial data transmit data transmit data mark state 1 frame sci3 operation user processing write data in tdr 1 figure 10.21 typical multiprocessor format transmit operation (8-bit data, multiprocessor bit added, and 1 stop bit) 242 receiving multiprocessor ddata: figure 10.22 shows a typical flow chart for receiving data using a multiprocessor format. after sci3 initialization, follow the procedure below. start set bit mpie in scr3 to 1 read bits oer and fer in ssr read bit rdrf in ssr rdrf = 1? read received data in rdr oer + fer = 1? read bits oer and fer in ssr continue receiving? end clear bit re in scr3 to 0 start receive error processing oer = 1? fer = 1? clear bits oer and fer in ssr to 0. overrun error processing break? framing error processing 1 2 1. 2. 4. 5. set bit mpie in serial control register 3 (scr3) to 1. read bits oer and fer in the serial status register (ssr) to determine if an error has occurred. if a receive error has occurred, receive error processing is executed. read ssr, check that bit rdrf = 1, then read received data from the receive data register (rdr). if a receive error occurs, read bits oer and fer in ssr to determine which error occurred. after the necessary error processing, be sure to clear the error flags to 0. data reception cannot resume while bit oer or fer is set to 1. when a framing error occurs, a break can be detected by reading the rxd pin value. no yes yes no yes no yes yes no no yes no error processing read received data in rdr a a end receive error processing own id? no read bit rdrf in ssr 4 oer + fer = 1? yes yes no rdrf = 1? no yes 5 3. if the received data does not match the id, set bit mpie to 1 again. bit rdrf is automatically cleared to 0 when data in the received data register (rdr) is read. read the serial status register (ssr) and confirm that rdrf = 1. if rdrf = 1, read the data in the received data register (rdr) and compare it with the processor? own id. 3 figure 10.22 typical flow chart for receiving serial data using multiprocessor format 243 figure 10.23 gives an example of data reception using a multiprocessor format. 0 d0 d1 d7 1 d0 d1 d7 0 1 10 1 start bit stop bit stop bit start bit receive data (id1) receive data (data 1) mark (idle state) mpie rdrf rdr value rxi request mpie cleared to 0 rdrf cleared to 0 no rxi request rdr state retained (a) data does not match own id 0 d0 d1 d7 1 d0 d1 d7 0 1 10 1 start bit stop bit stop bit start bit receive data (id2) receive data (data 2) mark (idle state) mpb mpb mpb mpb mpie rdrf rdr value id1 (b) data matches own id 1 frame 1 frame 1 frame 1 frame id1 if not own id, set mpie to 1 again sci3 operation user processing rxi request mpie cleared to 0 rdrf cleared to 0 if own id, continue receiving sci3 operation user processing rdrf cleared to 0 read data from rdr and set mpie to 1 again data 2 serial data serial data 1 1 rxi request read data from rdr id2 read data from rdr figure 10.23 example of multiprocessor format receive operation (8-bit data, multiprocessor bit added, and 1 stop bit) 244 10.3.7 interrupts sci3 has six interrupt sources: transmit end, transmit data empty, receive data full, and the three receive error interrupts (overrun error, framing error, and parity error). all share a common interrupt vector. table 10.16 describes each interrupt. table 10.16 sci3 interrupts interrupt interrupt request vector address rxi interrupt request due to receive data register full (rdrf) h'0024 txi interrupt request due to transmit data register empty (tdre) tei interrupt request due to transmit end (tend) eri interrupt request due to receive error (oer, fer, or per) the interrupt requests are enabled and disabled by bits tie and rie of scr3. when bit tdre in ssr is set to 1, txi is requested. when bit tend in ssr is set to 1, tei is requested. these two interrupt requests occur during data transmission. the initial value of bit tdre is 1. accordingly, if the transmit data empty interrupt request (txi) is enabled by setting bit tie to 1 in scr3 before placing transmit data in tdr, txi will be requested even though no transmit data has been readied. likewise, the initial value of bit tend is 1. accordingly, if the transmit end interrupt request (tei) is enabled by setting bit teie to 1 in scr3 before placing transmit data in tdr, tei will be requested even though no data has been transmitted. these interrupt features can be used to advantage by programming the interrupt handler to move the transmit data into tdr. when this technique is not used, the interrupt enable bits (tie and teie) should not be set to 1 until after tdr has been loaded with transmit data, to avoid unwanted txi and tei interrupts. when bit rdrf in ssr is set to 1, rxi is requested. when any of ssr bits oer, fer, or per is set to 1, eri is requested. these two interrupt requests occur during the receiving of data. details on interrupts are given in 3.3, interrupts. 245 10.3.8 application notes when using sci3, attention should be paid to the following matters. relation between bit tdre and writing data to tdr: bit tdre in the serial status register (ssr) is a status flag indicating that tdr does not contain new transmit data. tdre is automatically cleared to 0 when data is written to tdr. when sci3 transfers data from tdr to tsr, bit tdre is set to 1. data can be written to tdr regardless of the status of bit tdre. however, if new data is written to tdr while tdre is cleared to 0, assuming the data held in tdr has not yet been shifted to tsr, it will be lost. for this reason, it is recommended for securing serial data transmission that writing transmit data to tdr should be performed only once (not two or more times), always after confirming that bit tdre is set to 1. operation when multiple receive errors occur at the same time: when two or more receive errors occur at the same time, the status flags in ssr are set as shown in table 10.17. if an overrun error occurs, data is not transferred from rsr to rdr, and receive data is lost. table 10.17 ssr status flag states and transfer of receive data ssr status flags receive data transfer rdrf * oer fer per (rsr ? rdr) receive error status 1100 overrun error 0010 framing error 0001 parity error 1110 overrun error + framing error 1101 overrun error + parity error 0011 framing error + parity error 1111 overrun error + framing error + parity error : receive data transferred from rsr to rdr : receive data not transferred from rsr to rdr note: * rdrf keeps the same state as before the data was received. 246 break detection and processing: break signals can be detected by reading the rxd pin directly when a framing error (fer) is detected. in the break state the input from the rxd pin consists of all 0s, so fer is set and the parity error flag (per) may also be set. in the break state sci3 continues to receive, so if the fer bit is cleared to 0 it will be set to 1 again. sending a mark or break signal: when the txd bit in pmr6 is cleared to 0, the txd pin becomes an i/o port, the level and direction (input or output) of which are determined by the pdr and pcr bits. this feature can be used to place the txd pin in the mark state or to send a break signal. to place the serial communication line in the mark (1) state before te is set to 1, set the pdr and pcr bits both to 1. the txd pin becomes an i/o port outputting the value 1. to send a break signal during transmission, set the pcr bit to 1 and clear the pdr bit to 0, then clear the txd bit in pmr6 to 0. when the txd bit in pmr6 is cleared to 0, the txd pin becomes an i/o port outputting 0, regardless of the current transmission status. receive error flags and transmit operation (sysnchronous mode only): when a receive error flag (orer, per, or fer) is set to 1, sci3 will not start transmitting even if tdre is cleared to 0. be sure to clear the receive error flags to 0 when starting to transmit. note that clearing re to 0 does not clear the receive error flags. receive data sampling timing and receive margin in asynchronous mode: in asynchronous mode sci3 operates on a base clock with 16 times the bit rate frequency. in receiving, sci3 synchronizes internally with the falling edge of the start bit, which it samples on the base clock. receive data is latched at the rising edge of the eighth base clock pulse. see figure 10.24. 247 16 clock cycles 8 clock cycles start bit internal base clock receive data (rxd) synchronization sampling timing data sampling timing 07 15 7 150 d0 d1 0 figure 10.24 receive data sampling timing in asynchronous mode the receive margin in asynchronous mode can therefore be derived from the following equation. m = (0.5 ? ) ? ?(l ?0.5) f 100% ? ? 1 2n d ?0.5 n ...................... equation (1) m: receive margin (%) n: ratio of clock frequency to bit rate (n = 16) d: clock duty cycle (d = 0.5 to 1) l: frame length (l = 9 to 12) f: absolute value of clock frequency error in equation (1), if f (absolute value of clock frequency error) = 0 and d (clock duty cycle) = 0.5, the receive margin is 46.875% as given by equation (2) below. when d = 0.5 and f = 0, m = {0.5 ?1/(2 16)} 100% = 46.875% ....................................... equation (2) this value is theoretical. in actual system designs a margin of from 20 to 30 percent should be allowed. 248 relationship between bit rdrf and reading rdr: while sci3 is receiving, it checks the rdrf flag. if the rdrf flag is cleared to 0 when the reception of one frame of data is completed, data reception ends normally. if rdrf is set to 1, an overrun error occurs. rdrf is automatically cleared to 0 when the contents of rdr are read. if rdr is read more than once, the second and later reads will be performed with rdrf cleared to 0. note that when rdr is read while rdrf is 0, data from the next frame may be read if this reading operation is carried out at the same time that the reception of the next frame is completed. this is illustrated in figure 10.25. communica- tion line rdrf rdr frame 1 frame 2 frame 3 data 1 data 2 data 3 data 1 data 2 rdr read rdr read at (a), data 1 is read. at (b), data 2 is read. (a) (b) figure 10.25 relationship between data and rdr read timing to avoid the situation described above, rdr reading should be carried out only once (not two or more times) after confirming that bit rdrf is set to 1. when reading rdr more than once, be sure to copy any data read for the first time to ram, for example, and use the copied data. also note that rdr reading should be carried out with a safe margin just before reception of the next frame is completed. more concretely, rdr reading should be completed before transferring bit 7 in the synchronous mode or before transferring the stop bit in the asynchronous mode. 249 section 11 dtmf generator 11.1 overview the h8/3627 series has an on-chip dual-tone multifrequency (dtmf) generator that can generate dtmf signals. a dtmf signal accesses a telephone switching system by a pair of sine waves. figure 11.1 shows the frequency matrix. the dtmf generator generates frequencies corresponding to the numbers and symbols on the keypad of a telephone set or facsimile machine. 1 4 7 2 5 8 0 3 6 9 # a b c d r1 (697 hz) r2 (770 hz) r3 (852 hz) r4 (941 hz) c1 (1,209 hz) c2 (1,336 hz) c3 (1,477 hz) c4 (1,633 hz) figure 11.1 dtmf frequencies 250 11.1.1 features features of the dtmf generator are as follows. generates sine waves with dtmf frequencies from the system clock input at the osc pins (f osc ) the osc clock (1.2 mhz to 10 mhz, selectable in 400-khz steps) is divided to generate a 400-khz clock. input to a feedback loop with a modified programmable divider and sine-wave counter, this clock is used to generate sine waves with the dtmf frequencies. stable sine-wave output with low distortion sine waves are output from a high-precision resistor-ladder-type d/a converter. each cycle is divided into 32 segments to give a stable waveform with low distortion. composite or single waveform output register settings can select combined row-and-column-group output, or independent row- group or column-group output. 251 11.1.2 block diagram figure 11.2 shows a block diagram of the dtmf generator. dtlr clock counter 400 khz (1.2 mhz to 10 mhz, selectable in 400-khz steps) d/a sine-wave counter modified programmable divider dtcr feedback column section feedback toned vt ref f osc internal data bus row section dtlr: dtcr: dtmf load register dtmf control register d/a sine-wave counter modified programmable divider legend: figure 11.2 dtmf generator block diagram 252 11.1.3 pin configuration table 11.1 shows the pins assigned to the dtmf generator. table 11.1 pin configuration name abbrev. i/o function dtmf output reference level power supply pin vt ref reference level voltage for dtmf output dtmf signal output pin toned output dtmf signal output 11.1.4 register configuration table 11.2 shows the register configuration of the dtmf generator. table 11.2 register configuration name abbrev. r/w initial value address dtmf control register dtcr r/w h'40 h'ffb2 dtmf load register dtlr r/w h'e0 h'ffb3 253 11.2 register descriptions 11.2.1 dtmf control register (dtcr) bit 76543210 dten cloe rwoe clf1 clf0 rwf1 rwf0 initial value 01000000 read/write r/w r/w r/w r/w r/w r/w r/w dtcr is an 8-bit read/write register that enables the dtmf generator, enables row and column output, and selects the output frequencies. upon reset, dtcr is initialized to h'40. bit 7?tmf generator enable (dten): bit 7 enables or disables operation of the dtmf generator. bit 7: dten description 0 dtmf generator is halted (initial value) 1 dtmf generator operates bit 6?eserved bit: bit 6 is reserved: it is always read as 1, and cannot be modified. bit 5?olumn output enable (cloe): bit 5 enables or disables dtmf column signal output. bit 5: cloe description 0 dtmf column signal output is disabled (high-impedance) (initial value) 1 dtmf column signal output is enabled bit 4?ow output enable (rwoe): bit 4 enables or disables dtmf row signal output. bit 4: rwoe description 0 dtmf row signal output is disabled (high-impedance) (initial value) 1 dtmf row signal output is enabled 254 bits 3 and 2?tmf column signal output frequency 1 and 0 (clf1, clf0): bits 3 and 2 select the dtmf column signal frequency (c1 to c4). bit 3: clf1 bit 2: clf0 description 0 0 dtmf column signal output frequency: 1209 hz (c1) (initial value) 1 dtmf column signal output frequency: 1336 hz (c2) 1 0 dtmf column signal output frequency: 1447 hz (c3) 1 dtmf column signal output frequency: 1633 hz (c4) bits 1 and 0?tmf row signal output frequency 1 and 0 (rwf1, rwf0): bits 1 and 0 select the dtmf row signal frequency (r1 to r4). bit 1: rwf1 bit 0: rwf0 description 0 0 dtmf row signal output frequency: 697 hz (r1) (initial value) 1 dtmf row signal output frequency: 770 hz (r2) 1 0 dtmf row signal output frequency: 852 hz (r3) 1 dtmf row signal output frequency: 941 hz (r4) 255 11.2.2 dtmf load register (dtlr) bit 76543210 dtl4 dtl3 dtl2 dtl1 dtl0 initial value 11100000 read/write r/w r/w r/w r/w r/w dtlr is an 8-bit read/write register that specifies the ratio by which the clock frequency at the osc pins is divided for input to the dtmf generator. upon reset, dtlr is initialized to h'e0. bits 7 to 5?eserved bits: bits 7 to 5 are reserved: they are always read as 1, and cannot be modified. bits 4 to 0?sc clock division ratio 4 to 0 (dtl4 to dtl0): bits 4 to 0 specify a division ratio of the osc clock frequency which will generate a 400-khz clock for input to the dtmf generator. the ratio is set as a counter value from 3 to 25, corresponding to osc clock frequencies of 1.2 to 10 mhz (in 400-khz steps). description bit 4: dtl4 bit 3: dtl3 bit 2: dtl2 bit 1: dtl1 bit 0: dtl0 division ratio osc clock frequency 00000 illegal setting (initial value) 1 illegal setting 1 0 illegal setting 1 3 1.2 mhz 1004 1.6 mhz :::::: : 1100125 10 mhz 1 * illegal setting 1 ** illegal setting note: * don? care these bits must be set to the correct value. normal dtmf signal output frequencies will not be obtained if these bits are set to a value not matching the clock input at the osc pins. operation is not guaranteed if these bits are set to a value other than 3 to 25. 256 11.3 operation 11.3.1 output waveform the dtmf generator outputs a row-group or column-group sine wave (dtmf signal) or a combined row-column waveform at the toned pin. these signals are generated by a high- precision resistor-ladder-type d/a converter circuit. the output frequency is selected by dtcr. figure 11.3 shows an equivalent circuit for the toned output. figure 11.4 shows the output waveform of an independent row-group or column-group signal. one cycle of the output is divided into 32 segments, giving a stable output with low distortion. control output control row column vt gnd ref toned figure 11.3 equivalent circuit for toned output 1234567891011121314151617181920212223242526272829303132 time slot vt gnd ref figure 11.4 toned output waveform (independent row- or column-group output) 257 table 11.3 indicates the frequency deviation between the dtmf signals output by the dtmf generator and the nominal (standard) signal values. table 11.3 frequency deviation of dtmf signals from nominal signals symbol standard signal frequency (hz) dtmf signal output (hz) frequency deviation (%) r1 697 694.44 ?.37 r2 770 769.23 ?.10 r3 852 851.06 ?.11 r4 941 938.97 ?.22 c1 1209 1212.12 0.26 c2 1336 1333.33 ?.20 c3 1477 1481.48 0.30 c4 1633 1639.34 0.39 11.3.2 operation flow the procedure for using the dtmf generator is given below. 1. set the osc clock division ratio in dtlr to match the frequency of the connected system clock oscillator (1.2 mhz to 10 mhz in 400-khz steps). 2. select a row (r1 to r4) and/or column (c1 to c4) frequency with bits clf1, clf0, rwf1, and rwf0 in dtcr. 3. select row and/or column output with the cloe and rwoe bits in dtcr, and set the dten bit to 1 to enable the dtmf generator. this procedure outputs the selected dtmf signal from the toned pin. 258 11.4 typical use figure 11.5 shows an example of the use of the dtmf generator. toned vt ref p1 4 h8/3637 dtmf v mute ref1 ha16808ant 19 20 11 2 k w +0.47 f 100 k w 360 k w 24 k w 2sc458 note: numbers at ends of signal lines are pin numbers of ha16808ant. figure 11.5 connection to ha16808 ant 11.5 application notes when using the dtmf generator, note the following point: be sure that the dtlr setting (dtl4 to dtl0) matches the system clock frequency at the osc pins. normal dtmf signal output frequencies will not be obtained unless the dtlr setting matches the osc frequency. 259 section 12 a/d converter 12.1 overview the h8/3627 series includes on-chip a resistance-ladder-based successive-approximation analog- to-digital converter, and can convert up to two channels of analog input. 12.1.1 features the a/d converter has the following features. 8-bit resolution 2 input channels conversion time: approx. 12.4 m s per channel (at 5 mhz operation) built-in sample-and-hold function interrupt requested on completion of a/d conversion a/d conversion can be started by external trigger input 260 12.1.2 block diagram figure 12.1 shows a block diagram of the a/d converter. internal data bus amr adsr adrr control logic + com- parator an 6 an 7 adtrg v cc v ss multiplexer reference voltage irrad v cc v ss legend: amr: adsr: adrr: irrad: a/d mode register a/d start register a/d result register a/d converter interrupt request flag figure 12.1 block diagram of the a/d converter 12.1.3 pin configuration table 12.1 shows the a/d converter pin configuration. table 12.1 pin configuration name abbrev. i/o function power supply pin v cc input power supply ground pin v ss input ground and reference voltage analog input pin 6 an 6 input analog input channel 6 analog input pin 7 an 7 input analog input channel 7 external trigger input pin adtrg input external trigger input for starting a/d conversion 261 12.1.4 register configuration table 12.2 shows the a/d converter register configuration. table 12.2 register configuration name abbrev. r/w initial value address a/d mode register amr r/w h'10 h'ffc4 a/d start register adsr r/w h'7f h'ffc6 a/d result register adrr r undefined h'ffc5 12.2 register descriptions 12.2.1 a/d result register (adrr) bit 76543210 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 initial value undefined undefined undefined undefined undefined undefined undefined undefined read/write rrrrrrrr the a/d result register (adrr) is an 8-bit read-only register for holding the results of analog-to- digital conversion. adrr can be read by the cpu at any time, but the adrr values during a/d conversion are undefined. after a/d conversion is complete, the conversion result is stored in adrr as 8-bit data; this data is held in adrr until the next conversion operation starts. adrr is not cleared on reset. 262 12.2.2 a/d mode register (amr) bit 76543210 cks trge cks1 ch3 ch2 ch1 ch0 initial value 00010000 read/write r/w r/w r/w r/w r/w r/w r/w amr is an 8-bit read/write register for specifying the a/d conversion speed, external trigger option, and the analog input pins. upon reset, amr is initialized to h'10. bit 7?lock select (cks): bits cks and cks1 select the a/d conversion speed. conversion time bit 5: cks1 bit 7: cks conversion period ?= 2 mhz ?= 5 mhz 0 0 reserved (initial value) 1 124/ 62 m s 24.8 m s 1 0 62/ 31 m s 12.4 m s 1 31/ 15.5 m s * note: * operation is not guaranteed if the conversion time is less than 12.4 m s. set the bits to get a value of at least 12.4 m s. bit 6?xternal trigger select (trge): bit 6 enables or disables the start of a/d conversion by external trigger input. bit 6: trge description 0 disables start of a/d conversion by external trigger (initial value) 1 enables start of a/d conversion by rising or falling edge of external trigger at pin adtrg * note: * the external trigger ( adtrg ) edge is selected by bit ieg4 of the interrupt edge select register (iegr). see 3.3.2 for details. bit 5?lock select 1 (cks1): bits cks and cks1 select the a/d conversion speed. see bit 7, clock select (cks) for details. bit 4?eserved bit: bit 4 is reserved; it is always read as 1, and cannot be modified. 263 bits 3 to 0?hannel select 3 to 0 (ch3 to ch0): bits 3 to 0 select the analog input channel. the channel selection should be made while bit adsf is cleared to 0. bit 3: ch3 bit 2: ch2 bit 1: ch1 bit 0: ch0 analog input channel 00 ** no channel selected (initial value) 1 ** reserved 100 * reserved 10an 6 1an 7 1 ** reserved note: * don? care 12.2.3 a/d start register (adsr) bit 76543210 adsf initial value 01111111 read/write r/w the a/d start register (adsr) is an 8-bit read/write register for starting and stopping a/d conversion. a/d conversion is started by writing 1 to the a/d start flag (adsf) or by input of the designated edge of the external trigger signal, which also sets adsf to 1. when conversion is complete, the converted data is set in the a/d result register (adrr), and at the same time adsf is cleared to 0. bit 7?/d start flag (adsf): bit 7 controls and indicates the start and end of a/d conversion. bit 7: adsf description 0 read access indicates the completion of a/d conversion. (initial value) write access stops a/d conversion. 1 read access indicates a/d conversion in progress. write access starts a/d conversion. bits 6 to 0?eserved bits: bits 6 to 0 are reserved; they are always read as 1, and cannot be modified. 264 12.3 operation 12.3.1 a/d conversion operation the a/d converter operates by successive approximations, and yields its conversion result as 8-bit data. a/d conversion begins when software sets the a/d start flag (bit adsf) to 1. bit adsf keeps a value of 1 during a/d conversion, and is cleared to 0 automatically when conversion is complete. the completion of conversion also sets bit irrad in interrupt request register 2 (irr2) to 1. an a/d conversion end interrupt is requested if bit ienad in interrupt enable register 2 (ienr2) is set to 1. if the conversion time or input channel needs to be changed in the a/d mode register (amr) during a/d conversion, bit adsf should first be cleared to 0, stopping the conversion operation, in order to avoid malfunction. 12.3.2 start of a/d conversion by external trigger input the a/d converter can be made to start a/d conversion by input of an external trigger signal. external trigger input is enabled at pin adtrg when bit irq4 in port mode register 2 for the i/o port (pmr2) is set to 1, and bit trge in amr is set to 1. then when the input signal edge designated in bit ieg4 of the irq edge select register (iegr) is detected at pin adtrg , bit adsf in adsr will be set to 1, starting a/d conversion. figure 12.2 shows the timing. pin adtrg (when bit ieg4 = 0) adsf a/d conversion figure 12.2 external trigger input timing 265 12.4 interrupts when a/d conversion ends (adsf changes from 1 to 0), bit irrad in interrupt request register 2 (irr2) is set to 1. a/d conversion end interrupts can be enabled or disabled by means of bit ienad in interrupt enable register 2 (ienr2). for further details see 3.3, interrupts. 12.5 typical use an example of how the a/d converter can be used is given below, using channel 6 (pin an 6 ) as the analog input channel. figure 12.3 shows the operation timing. 1. bits ch3 to ch0 of the a/d mode register (amr) are set to 1010, making pin an 6 the analog input channel. a/d interrupts are enabled by setting bit ienad to 1, and a/d conversion is started by setting bit adsf to 1. 2. when a/d conversion is complete, bit irrad is set to 1 , and the a/d conversion result is stored in the a/d result register (adrr). at the same time adsf is cleared to 0, and the a/d converter goes to the idle state. 3. bit ienad = 1, so an a/d conversion end interrupt is requested. 4. the a/d interrupt handling routine starts. 5. the a/d conversion result is read and processed. 6. the a/d interrupt handling routine ends. if adsf is set to 1 again afterward, a/d conversion starts and steps 2 through 6 take place. figures 12.4 and 12.5 show flow charts of procedures for using the a/d converter. 266 idle a/d conversion (1) idle a/d conversion (2) idle interrupt (irrad) ienad adsf channel 4 (an 4 ) operation state adrr set * set * set * read conversion result read conversion result a/d conversion result (1) a/d conversion result (2) a/d conversion starts note: ( ) indicates instruction execution by software. * figure 12.3 typical a/d converter operation timing 267 start set a/d conversion speed and input channel perform a/d conversion? end yes no disable a/d conversion end interrupt start a/d conversion adsf = 0? no yes read adsr read adrr data figure 12.4 flow chart of procedure for using a/d converter (1) (polling by software) 268 start set a/d conversion speed and input channels enable a/d conversion end interrupt start a/d conversion a/d conversion end interrupt? yes no end yes no clear bit irrad to 0 in irr2 read adrr data perform a/d conversion? figure 12.5 flow chart of procedure for using a/d converter (2) (interrupts used) 12.6 application notes data in the a/d result register (adrr) should be read only when the a/d start flag (adsf) in the a/d start register (adsr) is cleared to 0. changing the digital input signal at an adjacent pin during a/d conversion may adversely affect conversion accuracy. 269 section 13 power supply circuit 13.1 overview the h8/3627 series incorporates an internal power supply step-down circuit. use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 v, independent of the voltage of the power supply connected to the external v cc pin. as a result, rise of the current consumption when an external power supply is used at 3.0 v or above can be held down. 13.2 configuration of the internal power supply step-down circuit connect the external power supply to the v cc pin, and connect a capacitance of approximately 0.1 m f between cv cc and v ss , as shown in figure 13.1. use without the capacitance may cause malfunction. note: in the external circuit interface, the external power supply voltage connected to v cc and the gnd potential connected to v ss are the reference levels. for example, for port input/output levels, the v cc level is the reference for the high level, and the v ss level is that for the low level. 270 c: capacitor with the standard power supply circuit configuration v ss v cc cv c cc step-down circuit internal logic internal power supply stabilization capacitance (approx. 0.1 m f) figure 13.1 power supply connection when internal step-down circuit is used 271 section 14 electrical characteristics 14.1 absolute maximum ratings table 14.1 lists the absolute maximum ratings. table 14.1 absolute maximum ratings item symbol value unit notes power supply voltage v cc , cv cc ?.3 to +7.0 v 1 reference level supply voltage vt ref ?.3 to v cc +0.3 v 1 programming voltage v pp ?.3 to +13.0 v 1 input voltage ports other than port b v in ?.3 to v cc +0.3 v 1 port b av in ?.3 to v cc +0.3 v 1 operating temperature t opr ?0 to +75 c1 storage temperature t stg ?5 to +125 c1 note: 1. permanent damage may occur to the chip if maximum ratings are exceeded. normal operation should be under the conditions specified in electrical characteristics. exceeding these values can result in incorrect operation and reduced reliability. 272 14.2 electrical characteristics 14.2.1 power supply voltage and operating range the power supply voltage and operating range are indicated by the shaded region in the figures below. note: caution is required during development, since the guaranteed operating ranges of the chip and development tools are different. power supply voltage vs. oscillator frequency range 10.0 2.7 2.2 * 4.0 5.5 v (v) cc f (mhz) osc 32.768 2.2 * 4.0 5.5 v (v) cc fw (khz) active mode (high and medium speeds) sleep mode all operating modes 5.0 2.0 note: * the oscillation start voltage is 2.5 v. 273 power supply voltage vs. clock frequency range 625.0 2.7 4.0 5.5 v (v) cc ?(khz) 5.0 2.7 2.2 4.0 5.5 v (v) cc ?(mhz) 16.384 2.2 4.0 5.5 v (v) cc ? (khz) sub active mode (high speed) sleep mode (except cpu) subactive mode subsleep mode (except cpu) watch mode (except cpu) active mode (medium speed) 8.192 4.096 2.5 0.5 500.0 312.5 62.5 analog power supply voltage vs. a/d converter operating range 2.7 2.2 4.0 5.5 v (v) cc ?(mhz) 2.7 4.0 5.5 v (v) cc ?(khz) 625.0 312.5 active (high speed) mode sleep mode active (medium speed) mode 500.0 5.0 2.5 0.5 62.5 274 14.2.2 dc characteristics table 14.2 lists the dc characteristics. table 14.2 dc characteristics v cc = 2.2 v to 5.5 v, v ss = 0.0 v, t a = ?0 to +75 c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note input high voltage v ih res , wkp 0 to wkp 7 , 0.8 v cc ? cc +0.3 v v cc = 2.7 v to 5.5 v irq 0 to irq 4 , tmif, tmig, sck 1 , sck 3 , adtrg 0.9 v cc ? cc +0.3 si 1 , rxd 0.7 v cc ? cc +0.3 v v cc = 2.7 v to 5.5 v 0.8 v cc ? cc +0.3 osc 1 v cc ?.5 v cc +0.3 v v cc = 2.7 v to 5.5 v v cc ?.3 v cc +0.3 p1 0 to p1 7 , p2 0 to p2 7 , p5 0 to p5 7 , p6 0 to p6 7 , 0.7 v cc ? cc +0.3 v v cc = 2.7 v to 5.5 v p7 0 to p7 7 , p8 0 to p8 7 , pa 1 to pa 3 , pb 6 , pb 7 0.8 v cc ? cc +0.3 input low voltage v il res , wkp 0 to wkp 7 , irq 0 to irq 4 , ?.3 0.2 v cc vv cc = 2.7 v to 5.5 v tmif, tmig, sck 1 , sck 3 , adtrg ?.3 0.1 v cc si 1 , rxd ?.3 0.3 v cc vv cc = 2.7 v to 5.5 v ?.3 0.2 v cc osc 1 ?.3 0.5 v v cc = 2.7 v to 5.5 v ?.3 0.3 note: connect pin test to v ss . 275 table 14.2 dc characteristics (cont) v cc = 2.2 v to 5.5 v, v ss = 0.0 v, t a = ?0 to +75 c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note input low voltage v il p1 0 to p1 7 , p2 0 to p2 7 , p5 0 to p5 7 , p6 0 to p6 7 , ?.3 0.3 v cc vv cc = 2.7 v to 5.5 v p7 0 to p7 7 , p8 0 to p8 7 , pa 1 to pa 3 , pb 6 , pb 7 ?.3 0.2 v cc output high voltage v oh p1 0 to p1 7 , p2 0 to p2 6 , p5 0 to p5 7 , v cc ?1.0 v v cc = 4.0 v to 5.5 v ? oh = 1.0 ma p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , v cc ?0.5 v cc = 4.0 v to 5.5 v ? oh = 0.5 ma pa 1 to pa 3 , v cc ?0.5 ? oh = 0.1 ma output low voltage v ol p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 1 to pa 3 , 0.5 v i ol = 0.4 ma p1 0 to p1 7 , p2 0 to p2 6 1.5 v cc = 4.0 v to 5.5 v i ol = 10 ma 0.6 v cc = 4.0 v to 5.5 v i ol = 1.6 ma 0.5 i ol = 0.4 ma 276 table 14.2 dc characteristics (cont) v cc = 2.2 v to 5.5 v, v ss = 0.0 v, t a = ?0 to +75 c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition note input |i il | res , p2 7 20 m av in = 0.5 v to 3 leakage 1 v cc ?0.5 v 2 current osc 1 , p1 0 to p1 7 , p2 0 to p2 6 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 1 to pa 3 , pb 6 , pb 7 1 m av in = 0.5 v to v cc ?0.5 v pull-up mos ? p p1 0 to p1 7 , p2 0 to p2 6 50 300 m av cc = 5 v, v in = 0 v current p5 0 to p5 7 , p6 0 to p6 7 ?5 v cc = 2.7 v, v in = 0 v reference value input capaci- tance c in all input pins except power supply pins 15 pf f = 1 mhz, v in = 0 v, t a = 25 c res 80 3 p2 7 50 notes: 2. applies to hd6433622, hd6433623, hd6433624, hd6433625, hd6433626, and hd6433627. 3. applies to hd6473627. 277 table 14.2 dc characteristics (cont) v cc = 2.2 v to 5.5 v, v ss = 0.0 v, t a = ?0 to +75 c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition notes active mode current dissipation i ope1 v cc 6 9 ma active mode (high speed), v cc = 5 v, f osc = 10 mhz 4, 5 i ope2 v cc 2 4 ma active mode (medium speed), v cc = 5 v, f osc = 10 mhz 4, 5 sleep mode current dissipation i sleep v cc 3.5 6 ma v cc = 5 v, f osc = 10 mhz 4, 5 subactive mode current dissipation i sub v cc ?230 m av cc = 2.7 v, 32-khz crystal oscillator ( sub = ?/2) 4, 5 ? m av cc = 2.7 v, 32-khz crystal oscillator ( sub = ?/8) reference value 4, 5 subsleep mode current dissipation i subsp v cc ? 15 m av cc = 2.7 v, 32-khz crystal oscillator ( sub = ?/2) 4, 5 watch mode current dissipation i watch v cc 6 m av cc = 2.7 v, 32-khz crystal oscillator 4, 5 standby mode current dissipation i stby v cc 5 m a 32-khz crystal oscillator not used 4, 5 ram data retaining voltage v ram v cc 2 v notes: 4. pin states during current measurement are shown below. mode other pins internal state oscillator pins active mode (high and mediumspeed) v cc operates system clock oscillator: crystal subclock oscillator: pin x 1 = v cc sleep mode v cc only timer operates subactive mode v cc operates system clock oscillator: crystal subsleep mode v cc only timer operates, cpu stops subclock oscillator: crystal watch mode v cc only time-base clock operates, cpu stops standby mode v cc cpu and timers all stop system clock oscillator: crystal subclock oscillator: pin x 1 = v cc 5. excludes current in pull-up mos transistors and output buffers. 278 table 14.2 dc characteristics (cont) v cc = 2.2 v to 5.5 v, v ss = 0.0 v, t a = ?0 to +75 c, including subactive mode, unless otherwise indicated. item symbol applicable pins min typ max unit test condition allowable output low current (per pin) i ol output pins except in ports 1 and 2 2 mav cc = 4.0 v to 5.5 v ports 1 and 2 10 v cc = 4.0 v to 5.5 v all output pins 0.5 allowable output low current (total) s i ol output pins except in ports 1 and 2 40mav cc = 4.0 v to 5.5 v ports 1 and 2 80 v cc = 4.0 v to 5.5 v all output pins 20 allowable output high ? oh all output pins 2 ma v cc = 4.0 v to 5.5 v current (per pin) 0.2 allowable output high s ? oh all output pins 15 ma v cc = 4.0 v to 5.5 v current (total) 10 279 14.2.3 ac characteristics table 14.3 lists the control signal timing, and tables 14.4 and 14.5 list the serial interface timing. table 14.3 control signal timing v cc = 2.2 v to 5.5 v, v ss = 0.0 v, t a = ?0 to +75 c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure system clock f osc osc 1 , osc 2 2 10 mhz v cc = 2.7 v to 5.5 v oscillation frequency 2 5 osc clock ( osc )t osc osc 1 , osc 2 100 1000 ns v cc = 2.7 v to 5.5 v 1 cycle time 200 1000 figure 14.1 system clock (? t cyc 2 16 t osc 1 cycle time 2000 ns subclock oscillation frequency f w x 1 , x 2 32.768 khz watch clock cycle time ( w ) t w x 1 , x 2 30.5 m s subclock ( sub ) cycle time t subcyc 2 8 t w 2 instruction cycle time 2 t cyc t subcyc oscillation stabiliza- tion time t rc osc 1 , osc 2 40 ms v cc = 4.0 v to 5.5 v (crystal oscillator) 60 v cc = 2.5 v to 5.5 v oscillation stabilization time t rc x 1 , x 2 2 s external clock high t cph osc 1 40 ns v cc = 2.7 v to 5.5 v figure 14.1 width 80 external clock low t cpl osc 1 40 ns v cc = 2.7 v to 5.5 v figure 14.1 width 80 external clock rise t cpr 15 ns v cc = 2.7 v to 5.5 v figure 14.1 time 20 external clock fall t cpf 15 ns v cc = 2.7 v to 5.5 v figure 14.1 time 20 pin res low width t rel res 18 t cyc t subcyc figure 14.2 notes: 1. a frequency between 1 mhz to 10 mhz is required when an external clock is input. 2. selected with sa1 and sa0 of system clock control register 2 (syscr2). 280 table 14.3 control signal timing (cont) v cc = 2.2 v to 5.5 v, v ss = 0.0 v, t a = ?0 to +75 c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure oscillation start vstart osc 1 , osc 2 2.5 v voltage x 1 , x 2 2.5 input pin high width t ih irq 0 to irq 4 , wkp 0 to wkp 7 , adtrg , tmif, tmig 2 t cyc t subcyc figure 14.3 input pin low width t il irq 0 to irq 4 , wkp 0 to wkp 7 , adtrg , tmif, tmig 2 t cyc t subcyc figure 14.3 281 table 14.4 serial interface timing (sci1) v cc = 2.2 v to 5.5 v, v ss = 0.0 v, t a = ?0 to +75 c, including subactive mode, unless otherwise specified. item symbol applicable pins min typ max unit test condition reference figure input serial clock cycle time t scyc sck 1 2 t cyc figure 14.4 input serial clock high width t sckh sck 1 0.4 t scyc figure 14.4 input serial clock low width t sckl sck 1 0.4 t scyc figure 14.4 input serial clock t sckr sck 1 60nsv cc = 4.0 v to 5.5 v figure 14.4 rise time 80 input serial clock t sckf sck 1 60nsv cc = 4.0 v to 5.5 v figure 14.4 fall time 80 serial output data t sod so 1 200 ns v cc = 4.0 v to 5.5 v figure 14.4 delay time 350 serial input data t sis si 1 200 ns v cc = 4.0 v to 5.5 v figure 14.4 setup time 400 serial input data t sih si 1 200 ns v cc = 4.0 v to 5.5 v figure 14.4 hold time 400 table 14.5 serial interface timing (sci3) v cc = 2.2 v to 5.5 v, v ss = 0.0 v, t a = ?0 to +75 c, including subactive mode, unless otherwise specified. item symbol min typ max unit test condition reference figure input clock cycle asynchronous t scyc 4 t cyc figure 14.5 synchronous 6 input clock pulse width t sckw 0.4 0.6 t scyc figure 14.5 transmit data delay time t txd 1 t cyc v cc = 4.0 v to 5.5 v figure 14.6 (synchronous mode) 1 receive data setup time t rxs 200 ns v cc = 4.0 v to 5.5 v figure 14.6 (synchronous mode) 400 receive data hold time t rxh 200 ns v cc = 4.0 v to 5.5 v figure 14.6 (synchronous mode) 400 282 14.2.4 a/d converter characteristics table 14.6 shows the a/d converter characteristics. table 14.6 a/d converter characteristics v cc = 2.2 v to 5.5 v, v ss = 0.0 v, t a = ?0 to +75 c, unless otherwise specified. item symbol applicable pins min typ max unit test condition notes analog input voltage av in an 6 , an 7 ?.3 v cc + 0.3 v analog input capacitance c ain an 6 , an 7 30 pf allowable signal source impedance r ain 10 k w resolution 8 bit non-linearity error 2.0 lsb quantization error 0.5 lsb absolute accuracy 2.5 lsb conversion time 12.4 248 m sv cc = 4.5 v to 5.5 v 24.8 248 m s 283 14.2.5 dtmf characteristics table 14.7 lists the dtmf generator characteristics. table 14.7 dtmf characteristics v cc = 2.2 v to 5.5 v, v ss = 0.0 v, t a = ?0 to +75?c, unless otherwise specified item symbol applicable pins min typ max unit test condition notes reference level supply voltage vt ref vt ref 2.2 v cc + 0.3 v dtmf output voltage (row) v or toned 550 723 mvrms vt ref ?gnd = 2.2 v r l = 100 k w figure 14.8 1 dtmf output voltage (column) v oc toned 567 760 mvrms vt ref ?gnd = 2.2 v r l = 100 k w figure 14.8 1 dtmf output distortion %disdt toned 3 7 % vt ref ?gnd = 2.2 v r l = 100 k w figure 14.8 dtmf output level db cr toned 2.5 db vt ref ?gnd = 2.2 v r l = 100 k w figure 14.8 notes: 1. v or and v oc indicate the output voltage during single wave output. 284 14.3 operation timing figures 14.1 to 14.6 show operation timings. t osc v ih v il t cph t cpl t cpr osc1 t cpf figure 14.1 system clock input timing res v il t rel figure 14.2 res low width timing v ih v il t il irq to irq wkp to wkp adtrg tmif, tmig t ih 04 07 figure 14.3 input timing 285 t scyc t sckf t sckl t sckh t sod v v oh ol * * t sis t sih sck so si 1 1 1 t sckr v or v ih oh * v or v il ol * notes: * output timing reference levels output high: output low: refer to figure 14.7 for output load condition. v = 2.0 v v = 0.8 v oh ol figure 14.4 serial interface 1 input/output timing 286 sck 3 t sckw t scyc figure 14.5 sck 3 input clock timing sck rxd (receive data) txd (transmit data) 3 t scyc t txd t rxh t rxs v or v ih oh * v or v il ol v oh v ol * * * notes: * output timing reference levels output high: output low: refer to figure 14.7 for output load condition. v = 2.0 v v = 0.8 v oh ol figure 14.6 input/output timing of serial interface 3 in synchronous mode 287 14.4 output load circuits figure 14.7 shows an output load condition. v cc 2.4 k w 12 k w 30 pf output pin figure 14.7 output load condition r l = 100 k w toned gnd figure 14.8 toned load circuit 288 289 appendix a cpu instruction set a.1 instructions operation notation rd8/16 general register (destination) (8 or 16 bits) rs8/16 general register (source) (8 or 16 bits) rn8/16 general register (8 or 16 bits) ccr condition code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #xx: 3/8/16 immediate data (3, 8, or 16 bits) d: 8/16 displacement (8 or 16 bits) @aa: 8/16 absolute address (8 or 16 bits) + addition subtraction multiplication ? division logical and logical or ? exclusive logical or ? move logical complement condition code notation symbol modified according to the instruction result * undefined (value not guaranteed) 0 always cleared to 0 not affected by the instruction execution result 290 table a.1 lists the h8/300l cpu instruction set. table a.1 instruction set mnemonic operation addressing mode/ instruction length (bytes) operand size #xx: 8/16 rn @rn @(d:16, rn) @?n/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states ihnzvc condition code ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mov.b #xx:8, rd mov.b rs, rd mov.b @rs, rd mov.b @(d:16, rs), rd mov.b @rs+, rd mov.b @aa:8, rd mov.b @aa:16, rd mov.b rs, @rd mov.b rs, @(d:16, rd) mov.b rs, @?d mov.b rs, @aa:8 mov.b rs, @aa:16 mov.w #xx:16, rd mov.w rs, rd mov.w @rs, rd mov.w @(d:16, rs), rd mov.w @rs+, rd mov.w @aa:16, rd mov.w rs, @rd mov.w rs, @(d:16, rd) mov.w rs, @?d mov.w rs, @aa:16 pop rd #xx:8 ? rd8 rs8 ? rd8 @rs16 ? rd8 @(d:16, rs16) ? rd8 @rs16 ? rd8 rs16+1 ? rs16 @aa:8 ? rd8 @aa:16 ? rd8 rs8 ? @rd16 rs8 ? @(d:16, rd16) rd16? ? rd16 rs8 ? @rd16 rs8 ? @aa:8 rs8 ? @aa:16 #xx:16 ? rd rs16 ? rd16 @rs16 ? rd16 @(d:16, rs16) ? rd16 @rs16 ? rd16 rs16+2 ? rs16 @aa:16 ? rd16 rs16 ? @rd16 rs16 ? @(d:16, rd16) rd16? ? rd16 rs16 ? @rd16 rs16 ? @aa:16 @sp ? rd16 sp+2 ? sp b b b b b b b b b b b b w w w w w w w w w w w 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 4 6 6 4 6 4 6 6 4 6 4 2 4 6 6 6 4 6 6 6 6 2 2 4 2 2 4 2 4 2 2 4 4 2 2 4 2 4 2 4 2 4 2 291 table a.1 instruction set (cont) mnemonic operation addressing mode/ instruction length (bytes) operand size #xx: 8/16 rn @rn @(d:16, rn) @?n/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states ihnzvc condition code ? ? push rs add.b #xx:8, rd add.b rs, rd add.w rs, rd addx.b #xx:8, rd addx.b rs, rd adds.w #1, rd adds.w #2, rd inc.b rd daa.b rd sub.b rs, rd sub.w rs, rd subx.b #xx:8, rd subx.b rs, rd subs.w #1, rd subs.w #2, rd dec.b rd das.b rd neg.b rd cmp.b #xx:8, rd cmp.b rs, rd cmp.w rs, rd mulxu.b rs, rd sp? ? sp rs16 ? @sp rd8+#xx:8 ? rd8 rd8+rs8 ? rd8 rd16+rs16 ? rd16 rd8+#xx:8 +c ? rd8 rd8+rs8 +c ? rd8 rd16+1 ? rd16 rd16+2 ? rd16 rd8+1 ? rd8 rd8 decimal adjust ? rd8 rd8?s8 ? rd8 rd16?s16 ? rd16 rd8?xx:8 ? ? rd8 rd8?s8 ? ? rd8 rd16? ? rd16 rd16? ? rd16 rd8? ? rd8 rd8 decimal adjust ? rd8 0?d ? rd rd8?xx:8 rd8?s8 rd16?s16 rd8 rs8 ? rd16 w b b w b b w w b b b w b b w w b b b b b w b 2 0? 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 14 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ? ? ? ? ? ? ? ? ? ? (1) ? ? ? ? (2) ? ? ? (2) ? ? ? ? ? ? ** (3) ? ? ? ? ? ? ? (1) ? ? ? ? (2) ? ? ? ? (2) ? ? ? ? ? ? ? ** ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (1) ? ? ? ? ? ? 292 table a.1 instruction set (cont) mnemonic operation addressing mode/ instruction length (bytes) operand size #xx: 8/16 rn @rn @(d:16, rn) @?n/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states ihnzvc condition code ? ? divxu.b rs, rd and.b #xx:8, rd and.b rs, rd or.b #xx:8, rd or.b rs, rd xor.b #xx:8, rd xor.b rs, rd not.b rd shal.b rd shar.b rd shll.b rd shlr.b rd rotxl.b rd rotxr.b rd rotl.b rd rotr.b rd rd16 ? rs8 ? rd16 (rdh: remainder, rdl: quotient) rd8 #xx:8 ? rd8 rd8 rs8 ? rd8 rd8 #xx:8 ? rd8 rd8 rs8 ? rd8 rd8 ? #xx:8 ? rd8 rd8 ? rs8 ? rd8 rd ? rd b b b b b b b b b b b b b b b b 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 (5) (6) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? b 7 b 0 0 c b 7 b 0 0 c c b 7 b 0 b 7 b 0 0c c b 7 b 0 c b 7 b 0 c b 7 b 0 c b 7 b 0 0 293 table a.1 instruction set (cont) mnemonic operation addressing mode/ instruction length (bytes) operand size #xx: 8/16 rn @rn @(d:16, rn) @?n/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states ihnzvc condition code ? bset #xx:3, rd bset #xx:3, @rd bset #xx:3, @aa:8 bset rn, rd bset rn, @rd bset rn, @aa:8 bclr #xx:3, rd bclr #xx:3, @rd bclr #xx:3, @aa:8 bclr rn, rd bclr rn, @rd bclr rn, @aa:8 bnot #xx:3, rd bnot #xx:3, @rd bnot #xx:3, @aa:8 bnot rn, rd bnot rn, @rd bnot rn, @aa:8 btst #xx:3, rd btst #xx:3, @rd btst #xx:3, @aa:8 btst rn, rd btst rn, @rd btst rn, @aa:8 (#xx:3 of rd8) ? 1 (#xx:3 of @rd16) ? 1 (#xx:3 of @aa:8) ? 1 (rn8 of rd8) ? 1 (rn8 of @rd16) ? 1 (rn8 of @aa:8) ? 1 (#xx:3 of rd8) ? 0 (#xx:3 of @rd16) ? 0 (#xx:3 of @aa:8) ? 0 (rn8 of rd8) ? 0 (rn8 of @rd16) ? 0 (rn8 of @aa:8) ? 0 (#xx:3 of rd8) ? (#xx:3 of rd8) (#xx:3 of @rd16) ? (#xx:3 of @rd16) (#xx:3 of @aa:8) ? (#xx:3 of @aa:8) (rn8 of rd8) ? (rn8 of rd8) (rn8 of @rd16) ? (rn8 of @rd16) (rn8 of @aa:8) ? (rn8 of @aa:8) (#xx:3 of rd8) ? z (#xx:3 of @rd16) ? z (#xx:3 of @aa:8) ? z (rn8 of rd8) ? z (rn8 of @rd16) ? z (rn8 of @aa:8) ? z b b b b b b b b b b b b b b b b b b b b b b b b 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 6 6 2 6 6 ? ? ? ? ? 294 table a.1 instruction set (cont) mnemonic operation addressing mode/ instruction length (bytes) operand size #xx: 8/16 rn @rn @(d:16, rn) @?n/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states ihnzvc condition code ? bld #xx:3, rd bld #xx:3, @rd bld #xx:3, @aa:8 bild #xx:3, rd bild #xx:3, @rd bild #xx:3, @aa:8 bst #xx:3, rd bst #xx:3, @rd bst #xx:3, @aa:8 bist #xx:3, rd bist #xx:3, @rd bist #xx:3, @aa:8 band #xx:3, rd band #xx:3, @rd band #xx:3, @aa:8 biand #xx:3, rd biand #xx:3, @rd biand #xx:3, @aa:8 bor #xx:3, rd bor #xx:3, @rd bor #xx:3, @aa:8 bior #xx:3, rd bior #xx:3, @rd bior #xx:3, @aa:8 bxor #xx:3, rd bxor #xx:3, @rd bxor #xx:3, @aa:8 bixor #xx:3, rd (#xx:3 of rd8) ? c (#xx:3 of @rd16) ? c (#xx:3 of @aa:8) ? c (#xx:3 of rd8) ? c (#xx:3 of @rd16) ? c (#xx:3 of @aa:8) ? c c ? (#xx:3 of rd8) c ? (#xx:3 of @rd16) c ? (#xx:3 of @aa:8) c ? (#xx:3 of rd8) c ? (#xx:3 of @rd16) c ? (#xx:3 of @aa:8) c (#xx:3 of rd8) ? c c (#xx:3 of @rd16) ? c c (#xx:3 of @aa:8) ? c c (#xx:3 of rd8) ? c c (#xx:3 of @rd16) ? c c (#xx:3 of @aa:8) ? c c (#xx:3 of rd8) ? c c (#xx:3 of @rd16) ? c c (#xx:3 of @aa:8) ? c c (#xx:3 of rd8) ? c c (#xx:3 of @rd16) ? c c (#xx:3 of @aa:8) ? c c ? (#xx:3 of rd8) ? c c ? (#xx:3 of @rd16) ? c c ? (#xx:3 of @aa:8) ? c c ? (#xx:3 of rd8) ? c b b b b b b b b b b b b b b b b b b b b b b b b b b b b 2 2 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 2 6 6 2 6 6 2 8 8 2 8 8 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 295 table a.1 instruction set (cont) mnemonic operation addressing mode/ instruction length (bytes) operand size #xx: 8/16 rn @rn @(d:16, rn) @?n/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states ihnzvc condition code ? bixor #xx:3, @rd bixor #xx:3, @aa:8 bra d:8 (bt d:8) brn d:8 (bf d:8) bhi d:8 bls d:8 bcc d:8 (bhs d:8) bcs d:8 (blo d:8) bne d:8 beq d:8 bvc d:8 bvs d:8 bpl d:8 bmi d:8 bge d:8 blt d:8 bgt d:8 ble d:8 jmp @rn jmp @aa:16 jmp @@aa:8 bsr d:8 jsr @rn jsr @aa:16 c ? (#xx:3 of @rd16) ? c c ? (#xx:3 of @aa:8) ? c pc ? pc+d:8 pc ? pc+2 if condition is true then pc ? pc+d:8 else next; b b 4 2 2 4 4 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 6 6 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 6 8 6 6 8 c z = 0 c z = 1 c = 0 c = 1 z = 0 z = 1 v = 0 v = 1 n = 0 n = 1 n ? v = 0 n ? v = 1 z (n ? v) = 0 z (n ? v) = 1 pc ? rn16 pc ? aa:16 pc ? @aa:8 sp? ? sp pc ? @sp pc ? pc+d:8 sp? ? sp pc ? @sp pc ? rn16 sp? ? sp pc ? @sp pc ? aa:16 ? branching condition 296 table a.1 instruction set (cont) mnemonic operation addressing mode/ instruction length (bytes) operand size #xx: 8/16 rn @rn @(d:16, rn) @?n/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states ihnzvc condition code jsr @@aa:8 rts rte sleep ldc #xx:8, ccr ldc rs, ccr stc ccr, rd andc #xx:8, ccr orc #xx:8, ccr xorc #xx:8, ccr nop eepmov sp? ? sp pc ? @sp pc ? @aa:8 pc ? @sp sp+2 ? sp ccr ? @sp sp+2 ? sp pc ? @sp sp+2 ? sp transit to sleep mode. #xx:8 ? ccr rs8 ? ccr ccr ? rd8 ccr #xx:8 ? ccr ccr #xx:8 ? ccr ccr ? #xx:8 ? ccr pc ? pc+2 if r4l 1 0 then repeat @r5 ? @r6 r5+1 ? r5 r6+1 ? r6 r4l? ? r4l until r4l=0 else next; b b b b b b 2 8 8 10 2 2 2 2 2 2 2 2 (4) 2 ? ? 2 ? ? ? ? 2 ? ? 2 ? ? ? ? ? ? 2 ? ? ? ? 2 ? ? 2 ? ? ? ? ? ? 2 ? ? ? ? ? ? 2 ? ? ? ? 2 4 notes: (1) set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0. (2) if the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0. (3) set to 1 if decimal adjustment produces a carry; otherwise retains value prior to arithmetic operation. (4) the number of states required for execution is 4n + 9 (n = value of r4l). (5) set to 1 if the divisor is negative; otherwise cleared to 0. (6) set to 1 if the divisor is zero; otherwise cleared to 0. 297 a.2 operation code map table a.2 is an operation code map. it shows the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. instruction when first bit of byte 2 (bit 7 of first instruction word) is 1. 298 table a.2 operation code map " # " # high low 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f nop bra mulxu bset shll shal sleep brn divxu bnot shlr shar stc bhi bclr rotxl rotl ldc bls btst rotxr rotr orc or bcc rts xorc xor bcs bsr bor bior bxor bixor band biand andc and bne rte ldc beq not neg bld bild bst bist add sub bvc bvs mov inc dec bpl jmp adds subs bmi eepmov mov cmp bge blt addx subx bgt jsr daa das ble mov add addx cmp subx or xor and mov mov * # note: bit-manipulation instructions the push and pop instructions are identical in machine language to mov instructions. * 299 a.3 number of execution states the following describes the operation status in each instruction provided for the h8/300 l cpu, as well as a calculation of the number of execution states. table a.4 gives the number of cycles (as the operation status) for such operations as an instruction fetch, data read/write performed during an instruction execution. table a.3 gives the number of execution states required for each cycle (operation status). the total number of states required for the execution of an instruction can be calculated by using the following equation: execution states = i s i + j s j + k s k + l s l + m s m + n s n examples: when instruction is fetched from on-chip rom, and an on-chip ram is accessed. 1. bset #0, @ff00 from table a.4: i = l = 2, j = k = m = n= 0 from table a.3: s i = 2, s l = 2 number of states required for execution = 2 2 + 2 2 = 8 when instruction is fetched from on-chip rom, branch address is read from on-chip rom, and on-chip ram is used for stack area. 2. jsr @@ 30 from table a.4: i = 2, j = k = 1, l = m = n = 0 from table a.3: s i = s j = s k = 2 number of states required for execution = 2 2 + 1 2+ 1 2 = 8 300 table a.3 number of cycles in each instruction execution status access location (instruction cycle) on-chip memory on-chip peripheral module instruction fetch s i 2 branch address read s j stack operation s k byte data access s l 2 or 3 * word data access s m internal operation s n 11 note: * depends on which on-chip module is accessed. see 2.9.1, notes on data access for details. 301 table a.4 number of cycles in each instruction instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n add add.b #xx:8, rd 1 add.b rs, rd 1 add.w rs, rd 1 adds adds.w #1, rd 1 adds.w #2, rd 1 addx addx.b #xx:8, rd 1 addx.b rs, rd 1 and and.b #xx:8, rd 1 and.b rs, rd 1 andc andc #xx:8, ccr 1 band band #xx:3, rd 1 band #xx:3, @rd 2 1 band #xx:3, @aa:8 2 1 bcc bra d:8 (bt d:8) 2 brn d:8 (bf d:8) 2 bhi d:8 2 bls d:8 2 bcc d:8 (bhs d:8) 2 bcs d:8 (blo d:8) 2 bne d:8 2 beq d:8 2 bvc d:8 2 bvs d:8 2 bpl d:8 2 bmi d:8 2 bge d:8 2 blt d:8 2 bgt d:8 2 ble d:8 2 bclr bclr #xx:3, rd 1 bclr #xx:3, @rd 2 2 bclr #xx:3, @aa:8 2 2 bclr rn, rd 1 302 table a.4 number of cycles in each instruction (cont) instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n bclr bclr rn, @rd 2 2 bclr rn, @aa:8 2 2 biand biand #xx:3, rd 1 biand #xx:3, @rd 2 1 biand #xx:3, @aa:8 2 1 bild bild #xx:3, rd 1 bild #xx:3, @rd 2 1 bild #xx:3, @aa:8 2 1 bior bior #xx:3, rd 1 bior #xx:3, @rd 2 1 bior #xx:3, @aa:8 2 1 bist bist #xx:3, rd 1 bist #xx:3, @rd 2 2 bist #xx:3, @aa:8 2 2 bixor bixor #xx:3, rd 1 bixor #xx:3, @rd 2 1 bixor #xx:3, @aa:8 2 1 bld bld #xx:3, rd 1 bld #xx:3, @rd 2 1 bld #xx:3, @aa:8 2 1 bnot bnot #xx:3, rd 1 bnot #xx:3, @rd 2 2 bnot #xx:3, @aa:8 2 2 bnot rn, rd 1 bnot rn, @rd 2 2 bnot rn, @aa:8 2 2 bor bor #xx:3, rd 1 bor #xx:3, @rd 2 1 bor #xx:3, @aa:8 2 1 bset bset #xx:3, rd 1 bset #xx:3, @rd 2 2 bset #xx:3, @aa:8 2 2 bset rn, rd 1 bset rn, @rd 2 2 303 table a.4 number of cycles in each instruction (cont) instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n bset bset rn, @aa:8 2 2 bsr bsr d:8 2 1 bst bst #xx:3, rd 1 bst #xx:3, @rd 2 2 bst #xx:3, @aa:8 2 2 btst btst #xx:3, rd 1 btst #xx:3, @rd 2 1 btst #xx:3, @aa:8 2 1 btst rn, rd 1 btst rn, @rd 2 1 btst rn, @aa:8 2 1 bxor bxor #xx:3, rd 1 bxor #xx:3, @rd 2 1 bxor #xx:3, @aa:8 21 cmp cmp. b #xx:8, rd 1 cmp. b rs, rd 1 cmp.w rs, rd 1 daa daa.b rd 1 das das.b rd 1 dec dec.b rd 1 divxu divxu.b rs, rd 1 12 eepmov eepmov 2 2n+2* 1 inc inc.b rd 1 jmp jmp @rn 2 jmp @aa:16 2 2 jmp @@aa:8 2 1 2 jsr jsr @rn 2 1 jsr @aa:16 2 1 2 jsr @@aa:8 2 1 1 ldc ldc #xx:8, ccr 1 ldc rs, ccr 1 note: n: initial value in r4l. the source and destination operands are accessed n + 1 times each. 304 table a.4 number of cycles in each instruction (cont) instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n mov mov.b #xx:8, rd 1 mov.b rs, rd 1 mov.b @rs, rd 1 1 mov.b @(d:16, rs), rd 21 mov.b @rs+, rd 1 1 2 mov.b @aa:8, rd 1 1 mov.b @aa:16, rd 2 1 mov.b rs, @rd 1 1 mov.b rs, @(d:16, rd) 21 mov.b rs, @?d 1 1 2 mov.b rs, @aa:8 1 1 mov.b rs, @aa:16 2 1 mov.w #xx:16, rd 2 mov.w rs, rd 1 mov.w @rs, rd 1 1 mov.w @(d:16, rs), rd 21 mov.w @rs+, rd 1 1 2 mov.w @aa:16, rd 2 1 mov.w rs, @rd 1 1 mov.w rs, @(d:16, rd) 21 mov.w rs, @?d 1 1 2 mov.w rs, @aa:16 2 1 mulxu mulxu.b rs, rd 1 12 neg neg.b rd 1 nop nop 1 not not.b rd 1 or or.b #xx:8, rd 1 or.b rs, rd 1 orc orc #xx:8, ccr 1 rotl rotl.b rd 1 rotr rotr.b rd 1 305 table a.4 number of cycles in each instruction (cont) instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n rotxl rotxl.b rd 1 rotxr rotxr.b rd 1 rte rte 2 2 2 rts rts 2 1 2 shal shal.b rd 1 shar shar.b rd 1 shll shll.b rd 1 shlr shlr.b rd 1 sleep sleep 1 stc stc ccr, rd 1 sub sub.b rs, rd 1 sub.w rs, rd 1 subs subs.w #1, rd 1 subs.w #2, rd 1 pop pop rd 1 1 2 push push rs 1 1 2 subx subx.b #xx:8, rd 1 subx.b rs, rd 1 xor xor.b #xx:8, rd 1 xor.b rs, rd 1 xorc xorc #xx:8, ccr 1 306 appendix b on-chip registers b.1 i/o registers (1) address register bit names module (low) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name h'90 h'91 h'92 h'93 h'94 h'95 h'96 h'97 h'98 pmr1 irq3 irq2 irq1 tmig tmofh tmofl tmow i/o ports h'99 pmr2 irq0 pof1 ncs so1 si1 sck1 irq4 h'9a pmr6 ?xd h'9b pmr5 wkp 7 wkp 6 wkp 5 wkp 4 wkp 3 wkp 2 wkp 1 wkp 0 h'9c pucr1 pucr1 7 pucr1 6 pucr1 5 pucr1 4 pucr1 3 pucr1 2 pucr1 1 pucr1 0 h'9d pucr2 pucr2 7 pucr2 6 pucr2 5 pucr2 4 pucr2 3 pucr2 2 pucr2 1 pucr2 0 h'9e pucr5 pucr5 7 pucr5 6 pucr5 5 pucr5 4 pucr5 3 pucr5 2 pucr5 1 pucr5 0 h'9f pucr6 pucr6 7 pucr6 6 pucr6 5 pucr6 4 pucr6 3 pucr6 2 pucr6 1 pucr6 0 h'a0 scr1 snc1 snc0 cks3 cks2 cks1 cks0 sci1 h'a1 scsr1 sol orer stf h'a2 sdru sdru7 sdru6 sdru5 sdru4 sdru3 sdru2 sdru1 sdru0 h'a3 sdrl sdrl7 sdrl6 sdrl5 sdrl4 sdrl3 sdrl2 sdrl1 sdrl0 h'a4 h'a5 h'a6 h'a7 h'a8 smr com chr pe pm stop mp cks1 cks0 sci3 h'a9 brr brr7 brr6 brr5 brr4 brr3 brr2 brr1 brr0 h'aa scr3 tie rie te re mpie teie cke1 cke0 legend: sci1: serial communication interface 1 sci3: serial communication interface 3 307 address register bit names module (low) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name h'ab tdr tdr7 tdr6 tdr5 tdr4 tdr3 tdr2 tdr1 tdr0 sci3 h'ac ssr tdre rdrf oer fer per tend mpbr mpbt h'ad rdr rdr7 rdr6 rdr5 rdr4 rdr3 rdr2 rdr1 rdr0 h'ae h'af h'b0 tma tma7 tma6 tma5 tma3 tma2 tma1 tma0 timer a h'b1 tca tca7 tca6 tca5 tca4 tca3 tca2 tca1 tca0 h'b2 dtcr dten cloe rwoe clf1 clf0 rwf1 rwf0 dtmf h'b3 dtlr dtl4 dtl3 dtl2 dtl1 dtl0 generator h'b4 h'b5 h'b6 tcrf tolh cksh2 cksh1 cksh0 toll cksl2 cksl1 cksl0 timer f h'b7 tcsrf ovfh cmfh ovieh cclrh ovfl cmfl oviel cclrl h'b8 tcfh tcfh7 tcfh6 tcfh5 tcfh4 tcfh3 tcfh2 tcfh1 tcfh0 h'b9 tcfl tcfl7 tcfl6 tcfl5 tcfl4 tcfl3 tcfl2 tcfl1 tcfl0 h'ba ocrfh ocrfh7 ocrfh6 ocrfh5 ocrfh4 ocrfh3 ocrfh2 ocrfh1 ocrfh0 h'bb ocrfl ocrfl7 ocrfl6 ocrfl5 ocrfl4 ocrfl3 ocrfl2 ocrfl1 ocrfl0 h'bc tmg ovfh ovfl ovie iiegs cclr1 cclr0 cks1 cks0 timer g h'bd icrgf icrgf7 icrgf6 icrgf5 icrgf4 icrgf3 icrgf2 icrgf1 icrgf0 h'be icrgr icrgr7 icrgr6 icrgr5 icrgr4 icrgr3 icrgr2 icrgr1 icrgr0 h'bf h'c0 h'c1 h'c2 h'c3 h'c4 amr cks trge cks1 ch3 ch2 ch1 ch0 a/d converter h'c5 adrr adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 h'c6 adsr adsf h'c7 h'c8 h'c9 h'ca h'cb h'cc 308 address register bit names module (low) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name h'cd h'ce h'cf h'd0 h'd1 h'd2 h'd3 i/o ports h'd4 pdr1 p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 h'd5 pdr2 p2 7 p2 6 p2 5 p2 4 p2 3 p2 2 p2 1 p2 0 h'd6 h'd7 h'd8 pdr5 p5 7 p5 6 p5 5 p5 4 p5 3 p5 2 p5 1 p5 0 i/o ports h'd9 pdr6 p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 h'da pdr7 p7 7 p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p7 0 h'db pdr8 p8 7 p8 6 p8 5 p8 4 p8 3 p8 2 p8 1 p8 0 h'dc h'dd pdra pa 3 pa 2 pa 1 h'de pdrb pb 7 pb 6 h'df h'e0 h'e1 h'e2 h'e3 i/o ports h'e4 pcr1 pcr1 7 pcr1 6 pcr1 5 pcr1 4 pcr1 3 pcr1 2 pcr1 1 pcr1 0 h'e5 pcr2 pcr2 7 pcr2 6 pcr2 5 pcr2 4 pcr2 3 pcr2 2 pcr2 1 pcr2 0 h'e6 h'e7 h'e8 pcr5 pcr5 7 pcr5 6 pcr5 5 pcr5 4 pcr5 3 pcr5 2 pcr5 1 pcr5 0 i/o ports h'e9 pcr6 pcr6 7 pcr6 6 pcr6 5 pcr6 4 pcr6 3 pcr6 2 pcr6 1 pcr6 0 h'ea pcr7 pcr7 7 pcr7 6 pcr7 5 pcr7 4 pcr7 3 pcr7 2 pcr7 1 pcr7 0 h'eb pcr8 pcr8 7 pcr8 6 pcr8 5 pcr8 4 pcr8 3 pcr8 2 pcr8 1 pcr8 0 h'ec h'ed pcra pcra 3 pcra 2 pcra 1 309 address register bit names module (low) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name h'ee h'ef h'f0 syscr1 ssby sts2 sts1 sts0 lson system h'f1 syscr2 nesel dton mson sa1 sa0 control h'f2 iegr ieg4 ieg3 ieg2 ieg1 ieg0 h'f3 ienr1 ienta iens1 ienwp ien4 ien3 ien2 ien1 ien0 h'f4 ienr2 iendt ienad ientg ientfh ientfl h'f5 h'f6 irr1 irrta irrs1 irri4 irri3 irri2 irri1 irri0 system h'f7 irr2 irrdt irrad irrtg irrtfh irrtfl control h'f8 h'f9 iwpr iwpf7 iwpf6 iwpf5 iwpf4 iwpf3 iwpf2 iwpf1 iwpf0 system control h'fa h'fb h'fc h'fd h'fe h'ff 310 b.2 i/o registers (2) mtcr?ultitone control register h'90 multitone generator register name address to which the register is mapped name of on-chip supporting module register acronym bit numbers initial bit values names of the bits. dashes (? indicate reserved bits. full name of bit descriptions of bit settings read only write only read and write r w r/w possible types of access bit initial value read/write 7 da0e 0 r/w 6 mten 0 r/w 5 dir 0 r/w 3 fr1 0 0 ft0 0 r/w 2 fr0 0 r/w 1 ft1 0 r/w 4 1 fine-tuning counter clock source select ft0 0 1 0 1 clock division ratio 1t osc (counter clock = f osc ) 2t osc (counter clock = f osc /2) 4t osc (counter clock = f osc /4) 8t osc (counter clock = f osc /8) ft1 0 0 1 1 frame counter clock source select fr0 0 1 0 1 clock division ratio 1t osc (counter clock = f osc ) 2t osc (counter clock = f osc /2) 4t osc (counter clock = f osc /4) 8t osc (counter clock = f osc /8) fr1 0 0 1 1 311 pmr1?ort mode register 1 h'98 i/o ports bit initial value read/write 7 irq3 0 r/w 6 irq2 0 r/w 5 irq1 0 r/w 4 0 3 tmig 0 r/w 0 tmow 0 r/w 2 tmofh 0 r/w 1 tmofl 0 r/w p1 /tmow pin function switch 0 functions as p1 i/o pin 1 functions as tmow output pin p1 /tmig pin function switch 0 functions as p1 i/o pin 1 functions as tmig input pin p1 /tmofl pin function switch 0 functions as p1 i/o pin 1 functions as tmofl output pin p1 /tmofh pin function switch 0 functions as p1 i/o pin 1 functions as tmofh output pin p1 /irq pin function switch p1 /irq pin function switch 1 0 functions as p1 i/o pin 1 functions as irq input pin 0 functions as p1 i/o pin 1 functions as irq input pin p1 /irq /tmif pin function switch 1 0 functions as p1 i/o pin 1 functions as irq /tmif input pin 0 3 1 2 5 6 7 0 3 1 2 5 6 7 1 2 3 1 2 3 312 pmr2?ort mode register 2 h'99 i/o ports bit initial value read/write 7 irq0 0 r/w 6 1 5 pof1 0 r/w 4 ncs 0 r/w 3 so1 0 r/w 0 irq4 0 r/w 2 si1 0 r/w 1 sck1 0 r/w p2 /sck pin function switch 0 functions as p2 i/o pin 1 functions as sck i/o pin p2 /si pin function switch 0 functions as p2 i/o pin 1 functions as si input pin tmig noise canceller select 0 noise canceller function not selected 1 noise canceller function selected p2 /so pin pmos control p2 /irq /adtrg pin function switch 1 0 cmos output 1 nmos open drain output 0 functions as p2 i/o pin 1 functions as irq /adtrg input pin 1 2 3 0 1 0 1 4 4 1 p2 /so pin function switch 1 0 functions as p2 i/o pin 1 functions as so output pin 3 3 1 1 1 1 2 1 p2 /irq pin function switch 1 0 functions as p2 input pin 1 functions as irq input pin 7 7 0 0 313 pmr6?ort mode register 6 h'9a i/o ports bit initial value read/write 7 1 6 1 5 1 r/w 4 1 r/w 3 1 0 0 r/w 2 txd 0 r/w 1 0 r/w p2 6 /txd pin function switch 1 0 functions as p2 6 i/o pin 1 functions as txd output pin pmr5?ort mode register 5 h'9b i/o ports bit initial value read/write 7 wkp 0 r/w 6 wkp 0 r/w 5 wkp 0 r/w 4 wkp 0 r/w 3 wkp 0 r/w 0 wkp 0 r/w 2 wkp 0 r/w 1 wkp 0 r/w 0 functions as p5 i/o pin 1 functions as wkp input pin n n 7 65432 10 p5 /wkp pin function switch nn (n = 7 to 0) pucr1?ort pull-up control register 1 h'9c i/o ports bit initial value read/write 7 pucr1 7 0 r/w 6 pucr1 6 0 r/w 5 pucr1 5 0 r/w 4 pucr1 4 0 r/w 3 pucr1 3 0 r/w 0 pucr1 0 0 r/w 2 pucr1 2 0 r/w 1 pucr1 1 0 r/w pucr2?ort pull-up control register 2 h'9d i/o ports bit initial value read/write 7 pucr2 7 0 r/w 6 pucr2 6 0 r/w 5 pucr 5 0 r/w 4 pucr 4 0 r/w 3 pucr 3 0 r/w 0 pucr 0 0 r/w 2 pucr 2 0 r/w 1 pucr 1 0 r/w 314 pucr5?ort pull-up control register 5 h'9e i/o ports bit initial value read/write 7 pucr5 7 0 r/w 6 pucr5 6 0 r/w 5 pucr5 5 0 r/w 4 pucr5 4 0 r/w 3 pucr5 3 0 r/w 0 pucr5 0 0 r/w 2 pucr5 2 0 r/w 1 pucr5 1 0 r/w pucr6?ort pull-up control register 6 h'9f i/o ports bit initial value read/write 7 pucr6 7 0 r/w 6 pucr6 6 0 r/w 5 pucr6 5 0 r/w 4 pucr6 4 0 r/w 3 pucr6 3 0 r/w 0 pucr6 0 0 r/w 2 pucr6 2 0 r/w 1 pucr6 1 0 r/w 315 scr1?erial control register 1 h'a0 sci1 bit initial value read/write 7 snc1 0 r/w 6 snc0 0 r/w 5 0 r/w 4 0 r/w 3 cks3 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w operation mode select clock source select 0 clock source is prescaler s, and pin sck is output pin 1 clock source is external clock, and pin sck is input pin 0 8-bit synchronous mode 16-bit synchronous mode 0 1 1 continuous clock output mode reserved 0 1 clock select bit 2 cks2 cks1 cks0 bit 1 bit 0 0 ?1024 ?256 1 1 0 ?64 ?32 1 ?16 100 1 ?8 00 ?4 10 1 ?2 ?= 5 mhz 204.8 s 51.2 s 12.8 s 6.4 s 3.2 s 1.6 s 0.8 s ?= 2.5 mhz 409.6 s 102.4 s 25.6 s 12.8 s 6.4 s 3.2 s 1.6 s 0.8 s synchronous transfer clock cycle 1 1 prescaler division 316 scsr1?erial control/status register 1 h'a1 sci1 bit initial value read/write 7 1 6 sol 0 r/w 5 orer 0 r/(w) 4 1 3 1 0 stf 0 r/w 2 1 1 0 r extended data bit overrun error flag 0 read write * start flag 0 indicates that transfer is stopped invalid 1 read write read write indicates transfer in progress starts a transfer operation 1 read write so 1 pin output level is low so 1 pin output level changes to low so 1 pin output level is high so 1 pin output level changes to high note: only a write of 0 for flag clearing is possible. * 0 [clearing condition] after reading 1, cleared by writing 0 1 [setting condition] set if a clock pulse is input after transfer is complete, when an external clock is used sdru?erial data register u h'a2 sci1 bit initial value read/write 7 sdru7 undefined r/w 6 sdru6 undefined r/w 5 sdru5 undefined r/w 4 sdru4 undefined r/w 3 sdru3 undefined r/w 0 sdru0 undefined r/w 2 sdru2 undefined r/w 1 sdru1 undefined r/w stores transmit and receive data 8-bit transfer mode: 16-bit transfer mode: not used upper 8 bits of data 317 sdrl?erial data register l h'a3 sci1 bit initial value read/write 7 sdrl7 undefined r/w 6 sdrl6 undefined r/w 5 sdrl5 undefined r/w 4 sdrl4 undefined r/w 3 sdrl3 undefined r/w 0 sdrl0 undefined r/w 2 sdrl2 undefined r/w 1 sdrl1 undefined r/w stores transmit and receive data 8-bit transfer mode: 16-bit transfer mode: 8-bit data lower 8 bits of data smr?erial mode register h'a8 sci3 bit initial value read/write 7 com 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 pm 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w parity enable 0 parity bit adding and checking disabled 1 parity bit adding and checking enabled clock select 0, 1 0 0 1 10 1 ?clock ?4 clock ?16 clock ?64 clock multiprocessor mode 0 multiprocessor communication function disabled 1 multiprocessor communication function enabled stop bit length 0 1 stop bit 1 2 stop bits parity mode 0 even parity 1 odd parity character length 0 8-bit data 1 7-bit data communication mode 0 asynchronous mode 1 synchronous mode 318 brr?it rate register h'a9 sci3 bit initial value read/write 7 brr7 1 r/w 6 brr6 1 r/w 5 brr5 1 r/w 4 brr4 1 r/w 3 brr3 1 r/w 0 brr0 1 r/w 2 brr2 1 r/w 1 brr1 1 r/w 319 scr3?erial control register 3 h'aa sci3 bit initial value read/write 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w clock enable cke1 bit 1 cke0 bit 0 description transmit end interrupt enable 0 transmit end interrupt (tei) disabled communication mode clock source sck pin function 3 1 transmit end interrupt (tei) enabled multiprocessor interrupt enable 0 multiprocessor interrupt request disabled (ordinary receive operation) 1 multiprocessor interrupt request enabled until a multiprocessor bit value of 1 is received, the receive data full interrupt (rxi) and receive error interrupt (eri) are disabled, and serial status register (ssr) flags rdrf, fer, and oer are not set. 0 0 asynchronous internal clock i/o port synchronous internal clock serial clock output 1 asynchronous internal clock clock output synchronous reserved 1 0 asynchronous external clock clock output synchronous external clock serial clock input 1 asynchronous reserved synchronous reserved [clearing condition] multiprocessor bit receives a data value of 1 transmit enable 0 transmit operation disabled (txd is the transmit data pin) 1 transmit operation enabled (txd is the transmit data pin) receive enable 0 receive operation disabled (rxd is a general i/o port) 1 receive operation enabled (rxd is the receive data pin) receive interrupt enable 0 receive data full interrupt request (rxi) and receive error interrupt request (eri) disabled 1 receive data full interrupt request (rxi) and receive error interrupt request (eri) enabled transmit interrupt enable 0 transmit data empty interrupt request (txi) disabled 1 transmit data empty interrupt request (txi) enabled reserved reserved reserved 320 tdr?ransmit data register h'ab sci3 bit initial value read/write 7 tdr7 1 r/w 6 tdr6 1 r/w 5 tdr5 1 r/w 4 tdr4 1 r/w 3 tdr3 1 r/w 0 tdr0 1 r/w 2 tdr2 1 r/w 1 tdr1 1 r/w data to be transferred to tsr 321 ssr?erial status register h'ac sci3 bit initial value read/write 7 tdre 1 r/(w) 6 rdrf 0 r/(w) 5 oer 0 r/(w) 4 fer 0 r/(w) 3 per 0 r/(w) 0 mpbt 0 r/w 2 tend 1 r 1 mpbr 0 r * * * * * note: * only a write of 0 for flag clearing is possible. 0 the multiprocessor bit in transmit data is 0 multiprocessor bit transmit 1 the multiprocessor bit in transmit data is 1 0 indicates reception of data in which the multiprocessor bit is 0 multiprocessor bit receive 1 indicates reception of data in which the multiprocessor bit is 1 0 indicates that transmission is in progress transmit end [clearing conditions] ? after reading tdre = 1, cleared by writing 0 to tdre. ? when data is written to tdr by an instruction. 1 indicates that a transmission has ended [setting conditions] ? when bit te in serial control register 3 (scr3) is 0. ? if tdre is set to 1 when the last bit of a transmitted character is sent. 0 indicates that data receiving is in progress or has been completed parity error [clearing conditions] after reading per = 1, cleared by writing 0 1 indicates that a parity error occurred in data receiving [setting conditions] when the sum of 1s in received data plus the parity bit does not match the parity mode bit (pm) setting in the serial mode register (smr) 0 indicates that data receiving is in progress or has been completed framing error [clearing conditions] after reading fer = 1, cleared by writing 0 1 indicates that a framing error occurred in data receiving [setting conditions] the stop bit at the end of receive data is checked and found to be 0 0 indicates that data receiving is in progress or has been completed overrun error [clearing conditions] after reading oer = 1, cleared by writing 0 1 indicates that an overrun error occurred in data receiving [setting conditions] when data receiving is completed while rdrf is set to 1 0 indicates there is no receive data in rdr receive data register full [clearing conditions] ? after reading rdrf = 1, cleared by writing 0. ? when data is read from rdr by an instruction. 1 indicates that there is receive data in rdr [setting conditions] when receiving ends normally, with receive data transferred from rsr to rdr 0 indicates that transmit data written to tdr has not been transferred to tsr transmit data register empty [clearing conditions] ? after reading tdre = 1, cleared by writing 0. ? when data is written to tdr by an instruction. 1 indicates that no transmit data has been written to tdr, or the transmit data written to tdr has been transferred to tsr [setting conditions] ? when bit te in serial control register 3 (scr3) is 0. ? when data is transferred from tdr to tsr. 322 rdr?eceive data register h'ad sci3 bit initial value read/write 7 rdr7 0 r 6 rdr6 0 r 5 rdr5 0 r 4 rdr4 0 r 3 rdr3 0 r 0 rdr0 0 r 2 rdr2 0 r 1 rdr1 0 r tma?imer mode register a h'b0 timer a bit initial value read/write 7 tma7 0 r/w 6 tma6 0 r/w 5 tma5 0 r/w 0 tma0 0 r/w 2 tma2 0 r/w 1 tma1 0 r/w internal clock select tma3 tma2 0 pss pss pss pss 0 4 1 clock output select 0 ?32 ?16 tma1 0 1 tma0 0 0 1 1 pss pss pss pss 10 1 0 0 1 1 1 psw psw psw psw 00 1 0 0 1 1 psw and tca are reset 10 1 0 0 1 1 prescaler and divider ratio or overflow period ?8192 ?4096 ?2048 ?512 ?256 ?128 ?32 ?8 1 s 0.5 s 0.25 s 0.03125 s interval timer time base function 0 0 1 ?8 ?4 10 1 1 00 1 10 1 ? /32 w ? /16 w ? /8 w ? /4 w 3 tma3 0 r/w 323 tca?imer counter a h'b1 timer a bit initial value read/write 7 tca7 0 r 6 tca6 0 r 5 tca5 0 r 4 tca4 0 r 3 tca3 0 r 0 tca0 0 r 2 tca2 0 r 1 tca1 0 r count value 324 dtcr?tmf control register h'b2 dtmf generator bit initial value read/write 7 dten 0 r/w 6 1 5 cloe 0 r/w 4 rwoe 0 r/w 3 clf1 0 r/w 0 rwf0 0 r/w 2 clf0 0 r/w 1 rwf1 0 r/w dtmf row signal output frequency 1 and 0 rwf0 0 1 0 1 dtmf row signal output frequency 697 hz (r1) 770 hz (r2) 852 hz (r3) 941 hz (r4) row output enable 0 1 dtmf row signal output is disabled (high-impedance) dtmf row signal output is enabled rwf1 0 1 dtmf column signal output frequency 1 and 0 clf0 0 1 0 1 dtmf column signal output frequency 1209 hz (c1) 1336 hz (c2) 1447 hz (c3) 1633 hz (c4) clf1 0 1 column output enable 0 1 dtmf column signal output is disabled (high-impedance) dtmf column signal output is enabled dtmf generator enable 0 1 dtmf generator is halted dtmf generator operates 325 dtlr?tmf load register h'b3 dtmf generator bit initial value read/write 7 1 6 1 5 1 4 dtl4 0 r/w 3 dtl3 0 r/w 0 dtl0 0 r/w 2 dtl2 0 r/w 1 dtl1 0 r/w osc clock division ratio 4 to 0 dtl3 0 0 0 0 0 1 1 1 division ratio illegal setting illegal setting illegal setting 3 4 25 illegal setting illegal setting dtl4 0 0 0 0 0 1 1 1 dtl2 0 0 0 0 1 0 0 1 dtl1 0 0 1 1 0 0 1 dtl0 0 1 0 1 0 1 osc clock frequency 1.2 mhz 1.6 mhz 10 mhz * * * (initial value) * note: don? care 326 tcrf?imer control register f h'b6 timer f bit initial value read/write 7 tolh 0 w 6 cksh2 0 w 5 cksh1 0 w 3 toll 0 w 0 cksl0 0 w 2 cksl2 0 w 1 cksl1 0 w 4 cksh0 0 w toggle output level h clock select l 0 1 00 1 10 1 internal clock: internal clock: internal clock: internal clock: ?32 ?16 ?4 note: don? care * external event (tmif): rising or falling edge ** ?2 toggle output level l 0 low level 1 high level clock select h 0 1 00 1 10 1 internal clock: internal clock: internal clock: internal clock: ?32 ?16 ?4 16-bit mode selected. tcfl overflow signals are counted. ** ?2 0 low level 1 high level 327 tcsrf?imer control/status register f h'b7 timer f bit initial value read/write 7 ovfh 0 r/(w) 6 cmfh 0 r/(w) 5 ovieh 0 r/w 4 cclrh 0 r/w 3 ovfl 0 r/(w) 0 cclrl 0 r/w 2 cmfl 0 r/(w) 1 oviel 0 r/w timer overflow flag h timer overflow interrupt enable l 0 [clearing condition] after reading ovfh = 1, cleared by writing 0 to ovfh 1 [setting condition] when the value of tcfh goes from h'ff to h'00 0 tcfl overflow interrupt disabled 1 tcfl overflow interrupt enabled timer overflow interrupt enable h compare match flag h 0 [clearing condition] after reading cmfh = 1, cleared by writing 0 to cmfh 1 [setting condition] when the tcfh value matches the ocrfh value 0 tcfh overflow interrupt disabled 1 tcfh overflow interrupt enabled counter clear h 0 16-bit mode: 8-bit mode: 1 tcf clearing by compare match disabled tcfh clearing by compare match disabled 16-bit mode: 8-bit mode: tcf clearing by compare match enabled tcfh clearing by compare match enabled timer overflow flag l 0 [clearing condition] after reading ovfl = 1, cleared by writing 0 to ovfl 1 [setting condition] when the value of tcfl goes from h'ff to h'00 compare match flag l 0 [clearing condition] after reading cmfl = 1, cleared by writing 0 to cmfl 1 [setting condition] when the tcfl value matches the ocrfl value counter clear l 0 tcfl clearing by compare match disabled 1 tcfl clearing by compare match enabled 328 tcfh?-bit timer counter fh h'b8 timer f bit initial value read/write 7 tcfh7 0 r/w 6 tcfh6 0 r/w 5 tcfh5 0 r/w 4 tcfh4 0 r/w 3 tcfh3 0 r/w 0 tcfh0 0 r/w 2 tcfh2 0 r/w 1 tcfh1 0 r/w count value tcfl?-bit timer counter fl h'b9 timer f bit initial value read/write 7 tcfl7 0 r/w 6 tcfl6 0 r/w 5 tcfl5 0 r/w 4 tcfl4 0 r/w 3 tcfl3 0 r/w 0 tcfl0 0 r/w 2 tcfl2 0 r/w 1 tcfl1 0 r/w count value ocrfh?utput compare register fh h'ba timer f bit initial value read/write 7 ocrfh7 1 r/w 6 ocrfh6 1 r/w 5 ocrfh5 1 r/w 4 ocrfh4 1 r/w 3 ocrfh3 1 r/w 0 ocrfh0 1 r/w 2 ocrfh2 1 r/w 1 ocrfh1 1 r/w ocrfl?utput compare register fl h'bb timer f bit initial value read/write 7 ocrfl7 1 r/w 6 ocrfl6 1 r/w 5 ocrfl5 1 r/w 4 ocrfl4 1 r/w 3 ocrfl3 1 r/w 0 ocrfl0 1 r/w 2 ocrfl2 1 r/w 1 ocrfl1 1 r/w 329 tmg?imer mode register g h'bc timer g bit initial value read/write 7 ovfh 0 r/(w) 6 ovfl 0 r/(w) 5 ovie 0 r/w 4 iiegs 0 r/w 3 cclr1 0 r/w 0 cks0 0 r/w 2 cclr0 0 r/w 1 cks1 0 r/w timer overflow flag h 0 [clearing condition] after reading ovfh = 1, cleared by writing 0 to ovfh 1 [setting condition] when the value of tcg overflows from h'ff to h'00 note: only a write of 0 for flag clearing is possible. * ** timer overflow interrupt enable timer overflow flag l 0 [clearing condition] after reading ovfl = 1, cleared by writing 0 to ovfl 1 [setting condition] when the value of tcg overflows from h'ff to h'00 0 tcg overflow interrupt disabled 1 tcg overflow interrupt enabled input capture interrupt edge select 0 interrupts are requested at the rising edge of the input capture signal 1 interrupts are requested at the falling edge of the input capture signal clock select 0 internal clock: internal clock: 0 1 internal clock: internal clock: 10 1 ?64 ?32 ?2 ? /2 w counter clear 0 tcg is not cleared tcg is cleared at the falling edge of the input capture signal 0 1 tcg is cleared at the rising edge of the input capture signal tcg is cleared at both edges of the input capture signal 10 1 330 icrgf?nput capture register gf h'bd timer g bit initial value read/write 7 icrgf7 0 r 6 icrgf6 0 r 5 icrgf5 0 r 4 icrgf4 0 r 3 icrgf3 0 r 0 icrgf0 0 r 2 icrgf2 0 r 1 icrgf1 0 r icrgr?nput capture register gr h'be timer g bit initial value read/write 7 icrgr7 0 r 6 icrgr6 0 r 5 icrgr5 0 r 4 icrgr4 0 r 3 icrgr3 0 r 0 icrgr0 0 r 2 icrgr2 0 r 1 icrgr1 0 r 331 amr?/d mode register h'c4 a/d converter bit initial value read/write 7 cks 0 r/w 6 trge 0 r/w 4 1 3 ch3 0 r/w 0 ch0 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w channel select no channel selected bit 3 0 bit 2 analog input channel ch3 ch2 0 ch1 ch0 bit 1 bit 0 * reserved 10 1 1 1 00 external trigger select 0 disables start of a/d conversion by external trigger 1 enables start of a/d conversion by rising or falling edge of external trigger at pin adtrg 5 cks1 0 r/w an 6 an 7 reserved ** 1 ** reserved clock select reserved bit 5 0 conversion period cks1 124/ 1 ?= 2 mhz 62 s ?= 5 mhz 24.8 s conversion time note: * operation is not guaranteed if the conversion time is less than 12.4 s. set bits 5 and 7 for a value of at least 12.4 s. don? care * bit 7 0 cks 0 62/ 0 31 s 12.4 s 1 31/ 1 15.5 s 1 * ** adrr?/d result register h'c5 a/d converter bit initial value read/write 7 adr7 undefined r 6 adr6 undefined r 5 adr5 undefined r 4 adr4 undefined r 3 adr3 undefined r 0 adr0 undefined r 2 adr2 undefined r 1 adr1 undefined r a/d conversion result 332 adsr?/d start register h'c6 a/d converter bit initial value read/write 7 adsf 0 r/w 6 1 5 1 4 1 3 1 0 1 2 1 1 1 a/d start flag 0 [read] indicates the completion of a/d conversion 1 [write] stops a/d conversion [read] indicates a/d conversion in progress [write] starts a/d conversion pdr1?ort data register 1 h'd4 i/o ports bit initial value read/write 7 p1 0 r/w 6 p1 0 r/w 5 p1 0 r/w 4 p1 0 r/w 3 p1 0 r/w 0 p1 0 r/w 2 p1 0 r/w 1 p1 0 r/w 76543 0 21 pdr2?ort data register 2 h'd5 i/o ports bit initial value read/write 7 p2 0 r/w 6 p2 0 r/w 5 p2 0 r/w 4 p2 0 r/w 3 p2 0 r/w 0 p2 0 r/w 2 p2 0 r/w 1 p2 0 r/w 76543 0 21 pdr5?ort data register 5 h'd8 i/o ports bit initial value read/write 7 p5 0 r/w 6 p5 0 r/w 5 p5 0 r/w 4 p5 0 r/w 3 p5 0 r/w 0 p5 0 r/w 2 p5 0 r/w 1 p5 0 r/w 30 21 4 5 6 7 333 pdr6?ort data register 6 h'd9 i/o ports bit initial value read/write 7 p6 0 r/w 6 p6 0 r/w 5 p6 0 r/w 4 p6 0 r/w 3 p6 0 r/w 0 p6 0 r/w 2 p6 0 r/w 1 p6 0 r/w 30 21 4 5 6 7 pdr7?ort data register 7 h'da i/o ports bit initial value read/write 7 p7 0 r/w 6 p7 0 r/w 5 p7 0 r/w 4 p7 0 r/w 3 p7 0 r/w 0 p7 0 r/w 2 p7 0 r/w 1 p7 0 r/w 30 21 4 5 6 7 pdr8?ort data register 8 h'db i/o ports bit initial value read/write 7 p8 0 r/w 6 p8 0 r/w 5 p8 0 r/w 4 p8 0 r/w 3 p8 0 r/w 0 p8 0 r/w 2 p8 0 r/w 1 p8 0 r/w 30 21 4 5 6 7 pdra?ort data register a h'dd i/o ports bit initial value read/write 7 1 6 1 5 1 4 1 3 pa 0 r/w 0 0 2 pa 0 r/w 1 pa 0 r/w 321 pdrb?ort data register b h'de i/o ports bit initial value read/write 7 pb r 6 pb r 5 4 3 0 2 1 6 7 334 pcr1?ort control register 1 h'e4 i/o ports bit initial value read/write 7 pcr1 0 w 6 pcr1 0 w 5 pcr1 0 w 4 pcr1 0 w 3 pcr1 0 w 0 pcr1 0 w 2 pcr1 0 w 1 pcr1 0 w port 1 input/output select 0 input pin 1 output pin 76543 0 21 pcr2?ort control register 2 h'e5 i/o ports bit initial value read/write note: as p2 7 is an input-only pin, it becomes a high-impedance output when pcr2 7 is set to 1. 7 pcr2 0 w 6 pcr2 0 w 5 pcr2 0 w 4 pcr2 0 w 3 pcr2 0 w 0 pcr2 0 w 2 pcr2 0 w 1 pcr2 0 w port 2 input/output select 0 input pin 1 output pin 76543 0 21 pcr5?ort control register 5 h'e8 i/o ports bit initial value read/write 7 pcr5 0 w 6 pcr5 0 w 5 pcr5 0 w 4 pcr5 0 w 3 pcr5 0 w 0 pcr5 0 w 2 pcr5 0 w 1 pcr5 0 w port 5 input/output select 0 input pin 1 output pin 76543 0 21 335 pcr6?ort control register 6 h'e9 i/o ports bit initial value read/write 7 pcr6 0 w 6 pcr6 0 w 5 pcr6 0 w 4 pcr6 0 w 3 pcr6 0 w 0 pcr6 0 w 2 pcr6 0 w 1 pcr6 0 w port 6 input/output select 0 input pin 1 output pin 76543 0 21 pcr7?ort control register 7 h'ea i/o ports bit initial value read/write 7 pcr7 0 w 6 pcr7 0 w 5 pcr7 0 w 4 pcr7 0 w 3 pcr7 0 w 0 pcr7 0 w 2 pcr7 0 w 1 pcr7 0 w port 7 input/output select 0 input pin 1 output pin 76543 0 21 pcr8?ort control register 8 h'eb i/o ports bit initial value read/write 7 pcr8 0 w 6 pcr8 0 w 5 pcr8 0 w 4 pcr8 0 w 3 pcr8 0 w 0 pcr8 0 w 2 pcr8 0 w 1 pcr8 0 w port 8 input/output select 0 input pin 1 output pin 76543 0 21 336 pcra?ort control register a h'ed i/o ports bit initial value read/write 7 1 6 1 5 1 4 1 3 pcra 0 w 0 1 2 pcra 0 w 1 pcra 0 w 32 1 port a input/output select 0 input pin 1 output pin syscr1?ystem control register 1 h'f0 system control bit initial value read/write 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 3 lson 0 r/w 0 1 2 1 1 1 4 sts0 0 r/w software standby 0 when a sleep instruction is executed in active mode, a transition is made to sleep mode. 1 standby timer select 2 to 0 0 wait time = 8,192 states wait time = 16,384 states 0 0 1 wait time = 32,768 states wait time = 65,536 states 10 1 1 * wait time = 131,072 states low speed on flag 0 the cpu operates on the system clock (? 1 the cpu operates on the subclock (? ) sub * when a sleep instruction is executed in subactive mode, a transition is made to subsleep mode. when a sleep instruction is executed in active mode, a transition is made to standby mode or watch mode. when a sleep instruction is executed in subactive mode, a transition is made to watch mode. note: don? care * 337 syscr2?ystem control register 2 h'f1 system control bit initial value read/write 7 1 6 1 5 1 3 dton 0 r/w 0 sa0 0 r/w 2 mson 0 r/w 1 sa1 0 r/w 4 nesel 0 r/w direct transfer on flag 0 when a sleep instruction is executed in active mode, a transition is made to standby mode, watch mode, or sleep mode. 1 when a sleep instruction is executed in subactive mode, a transition is made to watch mode or subsleep mode. when a sleep instruction is executed in active (high-speed) mode, a direct transition is made to active (medium-speed) mode if ssby = 0, mson = 1, and lson = 0, or to subactive mode if ssby = 1, tma3 = 1, and lson = 1. subactive mode clock select 0 /8 ? /4 0 1 1 /2 * w w w noise elimination sampling frequency select 0 sampling rate is ? /16 1 sampling rate is ? /4 osc osc when a sleep instruction is executed in active (medium-speed) mode, a direct transition is made to active (high-speed) mode if ssby = 0, mson = 0, and lson = 0, or to subactive mode if ssby = 1, tma3 = 1, and lson = 1. when a sleep instruction is executed in subactive mode, a direct transition is made to active (high-speed) mode if ssby = 1, tma3 = 1, lson = 0, and mson = 0, or to active (medium-speed) mode if ssby = 1, tma3 = 1, lson = 0, and mson = 1. medium speed on flag 0 operates in active (high-speed) mode 1 operates in active (medium-speed) mode note: don? care * 338 iegr?rq edge select register h'f2 system control bit initial value read/write 7 1 6 1 5 1 4 ieg4 0 r/w 3 ieg3 0 r/w 0 ieg0 0 r/w 2 ieg2 0 r/w 1 ieg1 0 r/w irq edge select 0 falling edge of irq pin input is detected 1 rising edge of irq pin input is detected 0 0 0 irq edge select 0 falling edge of irq pin input is detected 1 rising edge of irq pin input is detected 1 1 1 irq edge select 0 falling edge of irq pin input is detected 1 rising edge of irq pin input is detected 2 2 2 irq edge select 0 falling edge of irq /tmif pin input is detected 1 rising edge of irq /tmif pin input is detected 3 3 3 irq edge select 0 falling edge of irq /adtrg pin input is detected 1 rising edge of irq /adtrg pin input is detected 4 4 4 339 ienr1?nterrupt enable register 1 h'f3 system control bit initial value read/write 7 ienta 0 r/w 6 iens1 0 r/w 5 ienwp 0 r/w 4 ien4 0 r/w 3 ien3 0 r/w 0 ien0 0 r/w 2 ien2 0 r/w 1 ien1 0 r/w irq to irq interrupt enable 0 disables interrupt requests from irq to irq 1 4 4 0 0 enables interrupt requests from irq to irq 40 wakeup interrupt enable 0 disables interrupt requests from wkp to wkp 1 70 enables interrupt requests from wkp to wkp 70 sci1 interrupt enable 0 disables sci1 interrupts 1 enables sci1 interrupts timer a interrupt enable 0 disables timer a interrupts 1 enables timer a interrupts 340 ienr2?nterrupt enable register 2 h'f4 system control bit initial value read/write 7 iendt 0 r/w 6 ienad 0 r/w 5 0 4 ientg 0 r/w 3 ientfh 0 r/w 0 1 2 ientfl 0 r/w 1 0 timer fh interrupt enable 0 disables timer fh interrupts 1 enables timer fh interrupts timer fl interrupt enable 0 disables timer fl interrupts 1 enables timer fl interrupts timer g interrupt enable 0 disables timer g interrupts 1 enables timer g interrupts a/d converter interrupt enable 1 0 disables a/d converter interrupt requests 1 enables a/d converter interrupt requests direct transfer interrupt enable 1 0 disables direct transfer interrupt requests 1 enables direct transfer interrupt requests 341 irr1?nterrupt request register 1 h'f6 system control bit initial value read/write 7 irrta 0 r/w 6 irrs1 0 r/w 5 1 4 irri4 0 r/w 3 irri3 0 r/w 0 irri0 0 r/w 2 irri2 0 r/w 1 irri1 0 r/w timer a interrupt request flag 0 [clearing condition] when irrta = 1, it is cleared by writing 0 1 [setting condition] when the timer a counter overflows from h'ff to h'00 note: only a write of 0 for flag clearing is possible. * ** ** sci1 interrupt request flag 0 [clearing condition] when irrs1 = 1, it is cleared by writing 0 1 [setting condition] when an sci1 transfer is completed irq to irq interrupt request flag 0 [clearing condition] when irrin = 1, it is cleared by writing 0 to irrin. 1 [setting condition] when pin irq is set to interrupt input and the designated signal edge is detected. *** 40 n (n = 4 to 0) 342 irr2?nterrupt request register 2 h'f7 system control bit initial value read/write 7 irrdt 0 r/w 6 irrad 0 r/w 5 0 4 irrtg 0 r/w 3 irrtfh 0 r/w 0 1 2 irrtfl 0 r/w 1 0 direct transfer interrupt request flag 0 [clearing condition] when irrdt = 1, it is cleared by writing 0 1 [setting condition] a sleep instruction is executed when dton = 1 and a direct transfer is made note: only a write of 0 for flag clearing is possible. * ** ** * a/d converter interrupt request flag 0 [clearing condition] when irrad = 1, it is cleared by writing 0 1 [setting condition] when a/d conversion is completed and adsf is reset timer g interrupt request flag 0 [clearing condition] when irrtg = 1, it is cleared by writing 0 1 [setting condition] when pin tmig is set to tmig input and the designated signal edge is detected timer fh interrupt request flag 0 [clearing condition] when irrtfh = 1, it is cleared by writing 0 1 [setting condition] when counter fh matches output compare register fh in 8-bit mode, or when 16-bit counter f (tcfl, tcfh) matches 16-bit output compare register f (ocrfl, ocrfh) in 16-bit mode timer fl interrupt request flag 0 [clearing condition] when irrtfl = 1, it is cleared by writing 0 1 [setting condition] when tcfl matches in 8-bit mode 343 iwpr?akeup interrupt request register h'f9 system control bit initial value read/write 7 iwpf7 0 r/w 6 iwpf6 0 r/w 5 iwpf5 0 r/w 4 iwpf4 0 r/w 3 iwpf3 0 r/w 0 iwpf0 0 r/w 2 iwpf2 0 r/w 1 iwpf1 0 r/w note: only a write of 0 for flag clearing is possible. * ** ** wakeup interrupt request flag 0 [clearing condition] when iwpfn = 1, it is cleared by writing 0. 1 [setting condition] when pin wkp n is set to interrupt input and a falling signal edge is detected. *** * (n = 7 to 0) 344 appendix c i/o port block diagrams c.1 port 1 block diagrams sby (low level during reset and in standby mode) pucr1 7 pmr1 7 pdr1 7 pcr1 7 internal data bus pdr1: pcr1: pmr1: pucr1: port data register 1 port control register 1 port mode register 1 port pull-up control register 1 v cc v cc irq 3 timer f module tmif v ss p1 7 figure c.1 (a) port 1 block diagram (pin p1 7 ) 345 sby (low level during reset and in standby mode) pucr1 6 pmr1 6 pdr1 6 pcr1 6 internal data bus pdr1: pcr1: pmr1: pucr1: port data register 1 port control register 1 port mode register 1 port pull-up control register 1 v cc v cc irq 2 v ss p1 6 figure c.1 (b) port 1 block diagram (pin p1 6 ) 346 sby (low level during reset and in standby mode) pucr1 5 pmr1 5 pdr1 5 pcr1 5 internal data bus pdr1: pcr1: pmr1: pucr1: port data register 1 port control register 1 port mode register 1 port pull-up control register 1 v cc v cc irq 1 v ss p1 5 figure c.1 (c) port 1 block diagram (pin p1 5 ) 347 sby pucr1 4 pdr1 4 pcr1 4 internal data bus pdr1: pcr1: pucr1: port data register 1 port control register 1 port pull-up control register 1 v cc v cc v ss p1 4 figure c.1 (d) port 1 block diagram (pin p1 4 ) 348 sby pucr1 3 pmr1 3 pdr1 3 pcr1 3 internal data bus pdr1: pcr1: pmr1: pucr1: port data register 1 port control register 1 port mode register 1 port pull-up control register 1 tmig timer g module p1 3 v cc v cc v ss figure c.1 (e) port 1 block diagram (pin p1 3 ) 349 sby pucr1 n pmr1 n pdr1 n pcr1 n internal data bus tmofh (p1 2 ) tmofl (p1 1 ) pdr1: pcr1: pmr1: pucr1: n = 2, 1 port data register 1 port control register 1 port mode register 1 port pull-up control register 1 timer f module v cc p1 n v cc v ss figure c.1 (f) port 1 block diagram (pins p1 2 and p1 1 ) 350 sby pucr1 0 pmr1 0 pdr1 0 pcr1 0 internal data bus tmow pdr1: pcr1: pmr1: pucr1: port data register 1 port control register 1 port mode register 1 port pull-up control register 1 timer a module v cc p1 0 v cc v ss figure c.1 (g) port 1 block diagram (pin p1 0 ) 351 c.2 port 2 block diagrams pucr2 7 pmr2 7 pdr2 7 pcr2 7 internal data bus pdr2: pcr2: pmr2: pucr2: port data register 2 port control register 2 port mode register 2 port pull-up control register 2 irq 0 p2 7 figure c.2 (a) port 2 block diagram (pin p2 7 ) 352 sby pucr2 6 pmr6 2 pdr2 6 pcr2 6 internal data bus txd pdr2: pcr2: pmr6: pucr2: port data register 2 port control register 2 port mode register 6 port pull-up control register 2 sci3 module v cc p2 6 v cc v ss figure c.2 (b) port 2 block diagram (pin p2 6 ) 353 sby pucr2 5 pdr2 5 pcr2 5 re rxd pdr2: pcr2: pucr2: port data register 2 port control register 2 port pull-up control register 2 sci3 module v cc p2 5 v cc v ss internal data bus figure c.2 (c) port 2 block diagram (pin p2 5 ) 354 sby pdr2 4 pcr2 4 sckie sckoe scko scki pdr2: pcr2: pucr2: port data register 2 port control register 2 port pull-up control register 2 sci3 module p2 4 v cc v ss internal data bus v cc pucr2 4 figure c.2 (d) port 2 block diagram (pin p2 4 ) 355 sby pucr2 3 pmr2 3 pdr2 3 pcr2 3 internal data bus so pdr2: pcr2: pmr2: pucr2: port data register 2 port control register 2 port mode register 2 port pull-up control register 2 sci1 module v cc p2 3 v cc v ss 1 pmr2 3 figure c.2 (e) port 2 block diagram (pin p2 3 ) 356 sby pucr2 2 pmr2 2 pdr2 2 pcr2 2 internal data bus pdr2: pcr2: pmr2: pucr2: port data register 2 port control register 2 port mode register 2 port pull-up control register 2 si sci module p2 2 v cc v cc v ss figure c.2 (f) port 2 block diagram (pin p2 2 ) 357 sby pucr2 1 pmr2 1 pdr2 1 pcr2 1 exck scko scki pdr2: pcr2: pmr2: pucr2: port data register 2 port control register 2 port mode register 2 port pull-up control register 2 sci module v cc p2 1 v cc v ss internal data bus figure c.2 (g) port 2 block diagram (pin p2 1 ) 358 sby pucr2 0 pmr2 0 pdr2 0 pcr2 0 internal data bus pdr2: pcr2: pmr2: pucr2: port data register 2 port control register 2 port mode register 2 port pull-up control register 2 irq 4 p2 0 v cc v ss v cc a/d module adtrg figure c.2 (h) port 2 block diagram (pin p2 0 ) 359 c.3 port 5 block diagram sby pucr5 n pmr5 n pdr5 n pcr5 n internal data bus pdr5: pcr5: pmr5: pucr5: n = 0 to 7 port data register 5 port control register 5 port mode register 5 port pull-up control register 5 wkp n v cc p5 n v cc v ss figure c.3 port 5 block diagram 360 c.4 port 6 block diagram sby pucr6 n pdr6 n pcr6 n internal data bus pdr6: pcr6: pucr6: n = 0 to 7 port data register 6 port control register 6 port pull-up control register 6 v cc p6 n v cc v ss figure c.4 port 6 block diagram 361 c.5 port 7 block diagram sby pdr7 n pcr7 n internal data bus pdr7: pcr7: n = 0 to 7 port data register 7 port control register 7 p7 n v cc v ss figure c.5 port 7 block diagram 362 c.6 port 8 block diagram sby pdr8 n pcr8 n internal data bus pdr8: pcr8: n = 0 to 7 port data register 8 port control register 8 p8 n v cc v ss figure c.6 port 8 block diagram 363 c.7 port a block diagram sby pdra n pcra n internal data bus pdra: pcra: n = 1 to 3 port data register a port control register a pa n v cc v ss figure c.7 port a block diagram c.8 port b block diagram dec internal data bus amr0 to amr3 v a/d module in pb n n = 6, 7 figure c.8 port b block diagram 364 appendix d port states in the different processing states table d.1 port states overview port reset sleep subsleep standby watch subactive active p1 7 to p1 0 high impedance retained retained high impedance * retained functional functional p2 6 to p2 0 high impedance retained retained high impedance * retained functional functional p5 7 to p5 0 high impedance retained retained high impedance * retained functional functional p6 7 to p6 0 high impedance retained retained high impedance * retained functional functional p7 7 to p7 0 high impedance retained retained high impedance retained functional functional p8 7 to p8 0 high impedance retained retained high impedance retained functional functional pa 3 to pa 1 high impedance retained retained high impedance retained functional functional p2 7 , pb 7 , pb 6 high impedance high impedance high impedance high impedance high impedance high impedance high impedance note: * high level output when mos pull-up is in on state. 365 appendix e product line-up product type product code mark code package (hitachi package code) h8/3627 ztat standard hd6473627h hd6473627h 64-pin qfp (fp-64a) version products hd6473627fp hd6473627fp 64-pin lqfp (fp-64e) mask rom standard hd6433627h hd6433627( *** )h 64-pin qfp (fp-64a) version products hd6433627fp hd6433627( *** )fp 64-pin lqfp (fp-64e) h8/3626 mask rom standard hd6433626h hd6433626( *** )h 64-pin qfp (fp-64a) version products hd6433626fp hd6433626( *** )fp 64-pin lqfp (fp-64e) h8/3625 mask rom standard hd6433625h hd6433625( *** )h 64-pin qfp (fp-64a) version products hd6433625fp hd6433625( *** )fp 64-pin lqfp (fp-64e) h8/3624s mask rom standard hd6433624sh hd6433624s( *** )h 64-pin qfp (fp-64a) version products hd6433624sfp hd6433624s( *** )fp 64-pin lqfp (fp-64e) h8/3623s mask rom standard hd6433623sh hd6433623s( *** )h 64-pin qfp (fp-64a) version products hd6433623sfp hd6433623s( *** )fp 64-pin lqfp (fp-64e) h8/3622s mask rom standard HD6433622Sh HD6433622S( *** )h 64-pin qfp (fp-64a) version products HD6433622Sfp HD6433622S( *** )fp 64-pin lqfp (fp-64e) note: ( *** ) in mask rom versions is the rom code. 366 appendix f package dimensions dimensional drawings of the h8/3627 series in fp-64a, and fp-64e packages are shown in figure f.1, and f.2, respectively. hitachi code jedec eiaj weight (reference value) fp-64a conforms 1.2 g unit: mm *dimension including the plating thickness base material dimension 0.10 0.15 m 17.2 0.3 48 33 49 64 1 16 32 17 17.2 0.3 0.35 0.06 0.8 3.05 max 14 2.70 0 ?8 1.6 0.8 0.3 *0.17 0.05 0.10 +0.15 ?.10 1.0 *0.37 0.08 0.15 0.04 figure f.1 fp-64a package dimensions note: in case of inconsistencies arising within figures, dimensional drawings listed in the hitachi semiconductor packages manual take precedence and are considered correct. 367 hitachi code jedec eiaj weight (reference value) fp-64e conforms 0.4 g unit: mm *dimension including the plating thickness base material dimension m 12.0 0.2 10 48 33 116 17 32 64 49 *0.22 0.05 0.08 0.5 12.0 0.2 0.10 1.70 max *0.17 0.05 0.5 0.2 0 ?8 1.0 1.45 0.10 0.10 1.25 0.20 0.04 0.15 0.04 figure f.2 fp-64e package dimensions h8/3627 series hardware manual publication date: 1st edition, march 1999 published by: electronic devices business group hitachi, ltd. edited by: technical documentation group ul media co., ltd. co py ri g ht ?hitachi, ltd., 1999. all ri g hts reserved. printed in ja p an. |
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